Features

High -speed, 16 -bit parallel dual -cushioned interface

voltage output: ± 10V

13, 14, 14, 14 And 15 -bit linear level

16 -bit monotonous super temperature (L level)

Power consumption: maximum 600MW

gain gain And offset adjustment: Convenient to automatically calibrate the D/A converter

28- DIP and SOIC packaging

Description

DAC712

It is a complete 16 -bit resolution digital analog (D/A) converter with 16 -bit temperature monotonicity. DAC712 has accurate+10V temperature compensation benchmark voltage, ± 10V output amplifier and 16 -bit port bus interface.

The digital interface speed is fast, the minimum writing pulse width is 60ns, dual buffer, and has clear functions, which can reset the simulation output to bipolar zero.

The arrangement of the input of gain and offset adjustment makes them easy to be adjusted by the external D/A converter and the potential meter.

DAC712 has two linear error performance levels: ± 4lsb and ± 2LSB, and three different moving linear levels: ± 4LSB, ± 2LSB and ± 1LSB. The power voltage of the DAC712 is ± 12V and ± 15V.

DAC712 is packaged in a 28 -pin, 0.3 -inch wide plastic DIP and a wide -body plastic SOIC with a 28 -lead. DAC712P, U, PB, and UB are specified within the temperature range of -40 ° C to+85 ° C, and DAC712PK, UK, PL, and UL are specified within the range of 0 ° C to+70 ° C.

timing characteristics

Typical features

ta +25 ° C and VCC ± ± At 15V, unless there is another explanation.

Specification Discussion

Linear error

Linear error is defined as a straight line drawn between analog output and transmission characteristic endpoint deviation.

Micro -dividing linear error

Differential linear error (DLE) refers to the output change from one adjacent state to the next state. When the digital input code changes from a code to a adjacent code word, its output step is 1/2LSB ~ 3/2LSB. If DLE is greater than -1LSB, the D/A converter is considered monotonous.

monotonicity

If the output increases or remains unchanged in order to increase the digital input value, the D/A converter is monotonous. For performance level DAC712P/U, DAC712PB/UB, DAC712PK/UK, and DAC712PL/UL, the monotonicity of DAC712 is guaranteed within the specified temperature range, respectively, reaching 13, 14, 15, and 16 bits, respectively.

Settlement time

Stable time refers to the final value of the digital mode conversion output within the error range in the input change. For the output level of 20V and 1LSB, the set stability time is within the ± 0.003%range of the full marking range (FSR). The change of 1LSB is measured at the main advancement (FFFFH to 0000h, and 0000h to FFFFH: BTC code). This is the input conversion of the worst situation of the worst situation.

Total harmonic distortion+noise

Total harmonic distortion+noise is defined as the ratio of a square root to a square -meter root and base frequency value of harmonic and noise value. It is represented by the percentage of the influx amplitude of the FS under the sampling rate.

The signal -to -noise ratio and distortion rate (SINAD)

In addition to quantification and internal random noise power, SINAD also includes all harmonic components and prominent bandate components in the output noise power definition. Under the specified input frequency and sampling rate FS, Sinad is represented by DB.

Digital mold fault pulse

When the input is changed, the charge of the simulation output is injected into the simulation output from the digital input. Measure at the half -scale of the input code. At the input code, the state is changed from 7fffh to 8000H as much as possible.

Digital feedback

When the digital input high -frequency logic activity is not selected, the digital input high -frequency logic activity is coupled by device and displayed as output noise. This noise is digital feedback.

Operation

DAC712 is a single -chip integrated circuit, 16 -bit D/A converter, equipped with 16 -bit D/A converter switch and trapezoid network, voltage benchmark, output amplifier and micro micro Processor bus interface.

Interface logic

DAC712 has a dual -cushioning data lock. Enter the data locks to save a 16 -bit data word, and then load it to the second lock (D/A lock memory). This dual buffer structure allows to update multiple D/A converters at the same time. All digital control input low levels are effective. See the box diagram in Figure 8.

All locks are triggered horizontally. Enter the locks when the input is enabled as the logic 0 . When the input returns the logic 1 , the data is locked.

CLR input reset the input lock and D/A locks to provide bipolar zero output.

Logic input compatibility

DAC712 digital input compatible with TTL (1.4V switching level), with low leakage and high impedance input. Therefore, input is suitable for 5V logic drivers, such as 5VCMOS logic. The equivalent circuit of the digital input is shown in Figure 9.

If it is not connected, the data input floats to the logic 0 , and controls the input to float to the logic 0 . It is recommended to connect any unused input to DCOM to improve noise resistance.

When the power supply is closed, the digital input remains high impedance.

Input coding

DAC712 is designed as a positive binary dual -input code input codes (BTC) input codes compatible with bipolar simulation output operations. For bipolar analog output configuration, the digital input of 7fffH provides a full label output, 8000H gives a negative standard output, and 0000h gives bipolar zero output.

Internal reference

DAC712 contains+10V reference voltage.

The reference output can be used to drive the external load, and the source current is as high as 2mA. The load current should be constant, otherwise the gain and bipolar offset of the converter will change.

Output voltage

The output range of the output amplifier of the DAC712 is ± 10V. DAC712 provides ± 10V output swing when working under ± 11.4V or higher voltage power.

gain and offset adjustment

FIG. 10 illustrates the offset between the offset and gain adjustment of the bipolar connection D/A Adjustment of mutual influence. Table 1 shows the calibration value and code. The minimum range of these adjustments is ± 0.3%.

Disposal adjustment

The application generates the digital input code that generates the maximum negative output voltage, and adjust the offset potential or offset D. /A converter adjustment to -10v.

gain adjustment

The application provides digital input with a maximum positive voltage output. Adjust the gain potential or gain adjustment D/A converter to obtain the full standard voltage.

Installation

General precautions

Due to the high precision of these D/A converters, system design problems such as grounding and contact resistance have become very important. The 1LSB value of a 16 -bit converter with a scale of 20V is 305MV. When the load current is 5 μA, the series and connectors and the connector resistance will only cause a voltage drop of 300 μV. To understand the meaning of this system layout, the resistance of a typical 1 ounce copper printing circuit board (PCB) is 1/2m u0026#8486;/square meter. For a 5mA load, 10 dense ear (0.010 inches) with a width and 60 mm -inch printed circuit conductor will cause a voltage drop of 150 μV.

The analog output of the DAC712 has a LSB size of 305 μV (–96DB). Within the frequency range of interest, the noise base of the D/A converter must be kept below this level. DAC712 noise spectrum density (including noise generated by internal benchmarks) is shown in the typical characteristics.

The wiring connected to a high -resolution D/A converter should ensure that the best isolation is achieved with RF interference (RFI) and electromagnetic interference (EMI) source. The key to eliminating radio frequency radiation or pickup is a small loop area. Signal wires and backwriting should be kept together so that they have a small capture section of any external magnetic field. It is not recommended to use a steel wire wound structure.

Power and reference connection

The power supply container should be added as shown in Figure 11. In -vcc. Apply at a short period of critical settlement, you can use 0.01 μF AT -VCC and AT+VCC. The capacitor should be close to the packaging.

DAC712 has a separate simulation public pipe foot and digital public pipe foot. The current through DCOM is mainly switching transient, and the highest amplitude can reach 1mA. For all code, the current of ACOM is usually 5 μA.

Use separate simulation and digital grounding planes and single interconnection points to minimize the grounding circuit. Simulation feet are adjacent to each other, helping to isolate the analog signal from digital signals. The analog signal should stay away from the digital signal as much as possible and cross the right angle. Actual simulation ground plane around the D/A converter component and the simulation and power pins isolate the D/A converter from the switching current. It is recommended to connect DCOM and ACOM directly to the ground floor.

If multiple DAC712 is used, or if DAC712 shared power with other components, connect the ACOM and DCOM lines together once (instead of on each chip) to get better results.

Load connection

Since the reference point of VOUT and VREF OUT is ACOM pins, it is important to connect the D/A converter load directly to the ACOM pin; please refer to Figure 12.

Drivers resistance and contact resistance use R1 for R3. As long as the load resistance RL is constant, the R1 will only introduce an gain error, which can be eliminated by adjusting the gain adjustment of the D/A converter or the system range of the system range. If the output voltage is detected on ACOM, R2 is part of RL.

In some applications, it is impractical to return the load to the ACOM pins of the D/A converter. The output voltage detects the output voltage at the system location, because as long as R3 is requiredIt is a low -resistant layer or conductor, and the DAC712 ACOM current has not changed. In this case, DCOM can also be connected to the system ground.

gain and offset adjustment

Use potential meter connection

gain and offset adjustment pins provides external potential meter using external potential meter Filtering. The 15 -circle potential provision provides sufficient resolution. These fine -tuning adjustments are ± 0.3%of the full scale range; see Figure 13.

Use D/A converter

The gain adjustment and offset adjustment circuit of the DAC712 has been arranged so that these points can be easily driven by the external D/A converter; see Figure 14. The 12 -bit D/A converter provides offset adjustment resolution and gain adjustment resolution, and steps for 30 μV to 50 μV per LSB.

When the output of the D/A converter is about half scale+5V, the nominal value of the gain and offset appears.

The output voltage range is connected

The internal connection of the DAC712 output amplifier is used for ± 10V dual -pole (20V) output range. In other words, the bilateral shift resistor is connected to the internal reference voltage, and the 20V range resistor is connected to the VOUT. DAC712 cannot be connected for single operation.

(1), for no external adjustment, non -connected needle 4 and 6. The external resistor R1 to R4 tolerance is ± 1%. The adjustment range is at least ± 0.3%FSR.

(2), the proposed operation amplifier: OPA177GP, GS or OPA604AP, AU.

(3) The recommended operation amplifier: single OPA177GP, GS or dual OPA2604AP, AU.

(4) D/A converter: dual DAC7800 (serial input, 12 -bit resolution); dual DAC7801 (8 -bit port input, 12 -bit resolution); dual DAC7802 (12 digits (12 bits Port input, 12 -bit resolution); dual DAC7545 (12 -bit port input, 12 -bit resolution); or single DAC8043 (serial input, 12 -bit resolution). Double pole (complete): DAC813 (11 -bit resolution for 0V to+10V output; no computing amplifier).

Digital interface

Bus interface

DAC712 has 16 -bit, dual -buffering data bus interface and control line, which is convenient for 16 -bit bus interface. Dual buffer characteristics allow multiple D/A converters at the same time.

A0 is the enable control control of the data input lock.

A1 is the opening of D/A 闩 lock. WR is used to select data into locks enabled by A0 and A1. Reference Figure 8And the box diagram of Figure 1.

CLR sets the input data locks to full zero, and the D/A lock memory is set to provide bipolar 0V code at the output terminal of the D/A converter.

Single buffer operation

To use the DAC712 interface as a single buffer lock operation, the data input lock is connected to the DCOM permanently.If you are not required to enable the D/A converter, you should also connect it to DCOM.For this working mode, the width of the WR must be at least 80ns to enable the data to input the lock memory and enter the D/A lock.

By asserting A0, A1, and WR, and the high CLR high, the digital interface of DAC712 can be transparent.