Eight low RDSON data output

(at 25 ° C at IO 1A is 0.5 , VCC 5V ± 5%)

8 -bit serial input data (SPI)

8 -bit serial diagnostic output

overload and opening conditions

Output short circuit protection

ChipenableSelectFunction (low level effective)

The internal 36V clamping of each output

with another octagonal level

. Low static current (maximum 10mA)

.multiWatt15, POWERSO20 and SO20L [ 123]

L9822E is an octagonal low -pressure side solenoid valve driver focusing on multi -power BCD technology suitable for Australia's driving lights, relays and solenoid valves. DMOS surpasses L9822e with very low power consumption. The data is transmitted to the device serial peripheral interface (SPI) protocol. L9822 has the function of output status monitoring function.

[ 123] Equipment ground. This logical circuit and power output -level grounding device.

Reset

asynchronous reset L9822ESP's internal output level, parallel lock depositors and displacement registers.

This pin is in a low activation state and cannot be kept floating. The power -powered function can connect the pin to the VCC to the VCC with an external capacitor through an external resistor.

Chief Engineer

chip enabled. The data transmits from the shift register to the output end of the signal rising edge. The decline of the signal of the settings shifting register output voltage detection level comes from the output level. The output drive of the SO pin is enabled when this pin is low. So serial output. This pin is a shift register. When the CE is high, it is three -state. A The data position on this tube is high. It means that the special output is high. The low data bit on the pin means that the output is low. The diagnostic data provided by L9822 will be performed by comparing the serial output position with the previous one to compare the serial input position. Silicon serial input. This pin is serial data input. The climax is PIN, and a PARTICULARROUTPUTTBEOFF will be programmed. Just open for a while.

SCLK

Serial clock. This pin is a time -off register. New so data will appear on every rising data of this pin along the new data will beLock to each slk #39; s Fal Ling Edge to the displacement register. Output 00-07 Power output pins input and output correspond to 07 bits. First, the bus and 00 through the SPI are the last. The output terminal provides a flow limit and voltage sensor failure function instruction and protection. The output of the rated load current is 500mA, but the current limit is set to the minimum value of 1.05A. The output also has a car fixture to be set to about 36V for recycling load current.

Electrical features (VCC 5V ± 5%. Tj - 40 to 125 ° C; unless there are other regulations)

Electric characteristics (continued)

Serial peripheral interface (see Figure 2, time sequence diagram)

L9822ESPDMOS outputs a low -operated PORDEVICEFEATU ring, eight 1 RDSON DMOS drive output level has a transient protection circuit. Each channel is independently controlled by the output lock and the public reset line. Low -circuit protection and DC electricity of the driver, as well as resistance loads such as solenoid valves, lights and relays. Data is transmitted to the device protocol through these serial interfaces (SPI). The circuit is stored in the internal register through the serial input receiving 8 -bit serial data (SI) to control the output driver. Serial output (SO) provides 8 diagnostic data bits that represent voltage levels at the drive output end. This makes the microprocessor diagnose the condition of the output drive. The output saturation voltage can open a specific river reset line through the fault. This circuit can also be counted with other octagonal drives to block 8 multiple data. When the chip is enabled (CE), the device line is low. In addition, the (SO) is placed in a three -state mode to cancel the selection device. The active effect of the voltage level of the negative edge (CE) transmission drive on the mobile register and (CE) will be locked on the two drivers from the new data of the shift register. When the CE is low, the data bit is contained in the SCLK input in the SCLK input in the SI when each data bit is locked in the shift to the displacement register negative migration.

Internal block explanation

The internal architecture of the device is based on three internal main blocks: an octagonal displacement register for dialogue with the SPI bus, an octagonal lock of the control bit of the control bit of the device, and an octagonal loading loading Drive program group. The displacement register displacement register has serial and parallel input and serial and parallel output. The serial input AC receives data from Spibus, and the serial output sends the data to the SPI bus at the same time. This parallel output is locked on the parallel plate of AData's L9822ESPATTHEEND side. At the beginning of the data transmission cycle, the parallel input card diagnostic data is diagnosed to the shift register.

Parallel lock

Parallel lock depositors save the input data registration from shift. Then these data -driven output levels. The single register in the lock memory can be output during the overloaded failure condition. The entire lock is also cleared through the reset signal.

Output level

The output level provides active low -drive signals for 0.75A continuous load. Each output has a current restricted circuit output current at least 1.05A to allow high IN rapids. In addition, the inside of the output is set to 36 volts to make the inductive sensation transient when it is closed. Each output also has a voltage comparison table output node. If the voltage on the ON output pin exceeds 1.8V, the fault is the assumption and the lock -locking driving this specific stage reset to close the output to protect it. The description of this operation is as follows. These components also provide diagnostic feedback data to register for transformation. In addition, the comparator is the internal drop -down current of Tainan. If the output is turned off, the output pins are opened. The timing data transmission diagram 2 shows the use of the SPI bus.

CE high-low transition

When the chip enable (CE) pin is pulled down. TheTri-StateSerialoutPut (SO) pin driver will make the CE lower time. At the edge of the CE pin, the diagnostic data comes from the voltage comparator in the output stage. If the specific output is high, a logical signal will be plugged into the displacement register. If the output is low, the logic zero will be the most important bit (07) here (07) to display the serial input (SI) pin. A zero -legged foot will program out one output, and one will turn off the programming output.

SCLK transition

Then the serial clock (SCLK) pin should be pulled out. At this point, the diagnostic level from the most important output (07) will appear at the highest point here that the 07 pin is higher than 1.8V. Then lower the SCLK pin to high. The new SO data will appear SCLK and the new SI data after each edge will be locked to the L9822ESphift register to fall to the edge. ANUN limited amount of data can be shifted to the device (input Si pins, output SOPIN), allowing other SPI device grades to connect to a chrysanthemum chain and L9822ESP.

CE low to high change

Once the last data bit is moved to L9822ESP, CE sales should be raised. At the rising edge of the CE, the displacement register data is horizontal, and the output level will be driven by new data. The internal 160 μS delayed timer will also start (see Tuand) at the rising edge. During the 160μs period, the output will last for a period of time by the protection of analog restricted circuit due to faults. This reduced parts may flow immediately after overcoming Gao Yongliu. Once the delay has passed, the output voltage is through the comparator and any bodyThe output greater than 1.8 is performed to induced Warraracedorf. It should be noted that the two transmission positions of the SCLK pin at the CE pin should be low to avoid registering. Thethescrip input is controlled by the computer control.High CE pin.

Failure condition check

The fault can be checked in the following methods.Enter the new control bytes.Wait for 160 microseconds to stabilize the output.Time on the same controller and observe the diagnostic data of the device output.The diagnostic level should be poured in the first time.Any difference will open the output to the error.If the output is 0 and 1 as the diameter of the output, the output PIN is still very high and there are short circuit or overload.If the output is closed when the input is 1, a zero -as -the -diagnosis basis returns the output without pulling the output pins