Logic IC LTC1045CSW#TR The LTC1045 consists of six voltage converters and associated control circuits (see block diagram). Each decoder has a linear comparator input stage that outputs the positive input, respectively. The negative input of the first four comparison countries has something in common with VTRIP1, and the negative input of the last two comparison countries has something in common with VTRIP2. With these inputs, the switching point of the logic IC LTC1045CSW#TR comparator can be set anywhere within the common-mode range of V - to V+ - 2V. To improve noise immunity, the logic integrated circuit LTC1045CSW#TR has a small built-in hysteresis for each comparator. Hysteresis varies with bias current from 7mV for low bias current to 20mV for high bias current (see typical hysteresis vs. RSET curves). Setting the bias current is different from CMOS logic, any linear CMOS circuit must draw some quiescent current. A bias generator (block diagram) allows the comparator's quiescent current to vary. Logic IC LTC1045CSW#TR The bias current is programmed by an external resistor (see typical I+ vs RSET curve). As the bias current decreases, the LTC1045 slows down (see typical curve of delay time vs. RSET). In addition to setting the bias current, the ISET pin completely shuts down the power supply and locks the converter output. To do this, the ISET pin must be forced to V+ - 0.5V. As shown in Figure 4, CMOS gates or TTL gates with resistive pull-ups can do this well. Although the power drives the ISET pin with the logic in Figure 5. output driver

With the linear circuit turned off, the CMOS output logic powers up and holds the output state. With no DC load at the output, the power dissipation is zero. The latched output is very fast—typically 80ns from the rising edge of ISET. The material state is latched away slower-typically 1.5µs from the falling edge of ISET. This time is set by the power-on time of the comparator. During power-up, the output can assume a false state. To avoid problems, the output should not be considered valid until the falling edge of ISET 5µs after 2µs. When placing the outputs in the Hi-Z state, disabling the input sets the six outputs to a high impedance state. This allows the LTC1045 to be interfaced to the data bus. The output is high impedance when DISABLE = 1 and active when DISABLE = 0. Using a TTL supply, V+ = 4.5V to 5.5V and V - = GND, the disable input is TTL compatible.

There are four supplies on the LTC1045: V+, V-, VOH, and VOL. They can be connected almost arbitrarily, but with some limitations. There must be a minimum differential between V+ and V-, VOH and VOL, the differential between V+ and V- must be at least 4.5V, and the differential between VOH and VOL must be at least 3V. Another limitation is caused by the internal parasitic diode D1 (see Figure 5).