The programmable logic XC3S500E-4PQ208C Spartan-3E family architecture consists of 5 basic programmable functional elements: Configurable logic blocks (clbs) contain flexible look-up tables (luts) that implement logic and function as flip-flops or locks storage element of the memory. The programmable logic XC3S500E-4PQ208C clb performs various logic functions and stores data. • Input/Output Blocks (IOBs) control the flow of data between I/O pins and the device's internal logic. Each IOB supports bidirectional data flow and 3-state operations. Multiple signaling standards are supported, including four high-performance differential standards. The programmable logic XC3S500E-4PQ208C includes double data rate (DDR) registers. Block RAM provides data storage in the form of 18kbit dual port blocks. The programmable logic XC3S500E-4PQ208C? Multiplier block accepts two 18-bit binary numbers as input and computes the product.

• The Digital Clock Manager (DCM) block provides a self-calibrating, all-digital solution for distributing, delaying, multiplying, dividing, and phase-shifting clock signals. The organization of these elements is shown in Figure 1. A ring of IOBs surrounds a regular array of clbs. Each device has two columns of block RAM, except the XC3S100E has one column. Each RAM column consists of several 18 kbit RAM blocks. Each block RAM is associated with a dedicated multiplier. The DCMs are in the center, two at the top and two at the bottom of the device. The XC3S100E has only one DCM at the top and bottom, while the XC3S1200E and XC3S1600E add two DCMs in the middle of the left and right sides. The Spartan-3e family has a rich network of traces that interconnect all five functional elements, transmitting signals between them. Each functional element has an associated switch matrix, allowing multiple connections to be routed.

Spartan-3E FPGAs are programmed by loading configuration data into robust, reprogrammable static CMOS configuration latches (CCLs) that collectively control all functional elements and routing resources. The FPGA's configuration data is stored in an external PROM or some other non-volatile medium, either on-board or off-board. After power-up, use any of seven different modes to write configuration data to the FPGA: Master from Xilinx Serial Flash Platform Prom Serial Peripheral Interface (SPI) from an industry standard SPI Serial Flash Byte Peripheral Interface (BPI) or below industry standard x8 x 8/x16 Parallel and Flash? Slave Serial, usually from one processor? Download Slave Parallel, usually from one processor? Boundary Scan Download (JTAG), usually from one processor Or system download tester. In addition, Spartan-3E FPGAs support multi-boot configuration, allowing two or more FPGA configuration bitstreams to be stored in a parallel or flash memory. The FPGA application controls which configuration is loaded next and when.