The CPU LE80537LG0254MS LAET Intel Core™ 2 Dual Processor based on 65nm process technology is the next-generation high-performance, low-power processor based on Intel Core™ microarchitecture. The Intel Core 2 dual-core processor supports systems based on the mobile Intel® 965 Express chipset and Intel® 82801HBM ICH8M controller hub. This document contains electrical, mechanical, and thermal specifications for the following processors: Intel Core 2 Duo - Standard Voltage? Intel Core 2 Duo - Low Voltage? Intel Core 2 Duo - Ultra Low Voltage? Intel Core 2 Duo Extreme Processing device

Note: In this document, the Intel Core 2 Duo and Intel Core 2 Extreme processors are referred to as processors, while the Mobile Intel® 965 Express chipset family is referred to as (G)MCH.

The following list provides some of the key features of this processor: ? Mobility with enhanced performance ? Intel Dual-Core Processor Architecture with Intel ? Wide Dynamic Execution 32 kb write-back data cache per core? On-die up to 4 mb L2 cache Shared cache with advanced transport architecture? Streaming SIMD Extension 2 (SSE2), Streaming SIMD Extension 3 (SSE3) and Supplementary Streaming SIMD Extension 3 (SSSE3)? 800 mhz Source Synchronous Front Side Bus (FSB) for Intel Core 2 Extreme processors, Intel Core 2 Duo dual standard and low voltage processors. 533-MHz FSB Advanced power management features for Intel Core 2 Duo ULV processors, including enhanced Intel SpeedStep™ technology and dynamic FSB frequency switching. ?Intel Enhanced Deep Sleep State with P_LVL5 I/O Support?Digital Temperature Sensor (DTS)?Intel?64 Technology?Enhanced Intel?Virtualization Technology?Intel?Dynamic Boost Technology?Enhanced Multi-Thread Thermal Management(EMTTM)?PSI2 Capability? Standard voltage processors are available in Micro-FCPGA and Micro-FCBGA packages. Low-voltage and ultra-low-voltage processors are only available in MicroFCBGA packages. Intel Core 2 Extreme processors are only available in micro-fcpga packages. ? Execute disable bit support for enhanced security

The CPU LE80537LG0254MS LAET processor supports single core-level and packet-level low-power states for optimal power management.

The CPU LE80537LG0254MS LAET core can independently enter the C1/AutoHALT, C1/MWAIT, C2, C3 and C4 low power states. When both cores are in a common core low power state at the same time, the central power management logic reads into the chipset by initiating a P_LVLx (P_LVL2, P_LVL3, P_LVL4 or P_LVL5) I/O, and the CPU LE80537LG0254MS LAET ensures that the entire processor enters Corresponding package low power state.

The CPU LE80537LG0254MS LAET processor implements two software interfaces for requesting low-power states: the CPU LE80537LG0254MS LAET MWAIT instruction extension with sub-state hints or P_LVLx read into the processor I/O address space mapping The ACPI P_BLK register block. P_LVLx I/O reads are translated to the equivalent MWAIT C-state request inside the processor and do not directly result in an I/O read on the processor FSB.