Programmable Logic EPM7160STC100-10 Open Channel Output Option for MAX 7000s Devices Programmable Logic EPM7160STC100-10 Programmable Macrocell with Individual Clear Flip-Flops, Preset, Clock, Clock and Enable Programmable Logic EPM7160STC100-10 Programmable Control Power saving mode reduces over 50% in each macrocell Configurable expander product-term distribution, allowing up to 32 product terms/macrocell 44 to 208 pins available Plastic J-lead chip carrier (PLCC), ceramic pin mesh Array (PGA), Plastic Quad Flat Package (PQFP), Programmable Logic EPM7160STC100-10 Power Quad Flat Package (RQFP), Programmable Security Bit Protection Patented Design 3.3V or 5.0V Operation - Multiple OLTTM I/O Interface Operation , allows devices to interface with 3.3 or 5.0V devices (MultiVolt I/O operation is not available in 44-pin packages) - pin compatible with low voltage 7000 MAX and MAX 7000 b devices Enhanced features on MAX 7000 e and 7000S MAX devices - 6 Pin or logic-driven allows output signals - two global clock signals with optional inversion - Enhanced interconnect resources for improved routability Fast input setup times Provides dedicated paths from I/O pins to macrocell registers Software design support , Altera Development System provides automatic location and routing for Windows-based PCs and Sun SPARCstations, as well as HP 9000 series 700/800 workstations

• 7000 devices contain 32 to 256 macrocells that are grouped into groups of 16 macrocells called logic array blocks (labs). Each macrocell has a programmable and/fixed or array, and a configurable register with independent programmable clock, clock enable, clear and preset functions. To build complex logic functions, each macrocell can be supplemented with shareable expander items and high-speed parallel expander items, with up to 32 items per macrocell.

The MAX 7000 series offers programmable speed/power optimization. Speed-critical parts of the design can run at high speed/full power while the rest run at low speed/low power. This speed/power optimization feature enables designers to configure one or more macrosleeves to run at 50% or less power, while adding only a nominal time delay. The MAX 7000E and MAX 7000S devices also offer an option to reduce the rotational speed of the output buffer to minimize noise transients when switching non-speed-critical signals. The output drivers for all MAX 7000 devices (except 44-pin devices) can be set to operate at 3.3 v or 5.0 v, allowing the MAX 7000 devices to be used in mixed-voltage systems.

The MAX 7000 family is supported by the Altera Development System, which provides integration of schematic, text (including VHDL, Verilog HDL, and Altera Hardware Description Language (AHDL)) and waveform design entry, compilation and logic synthesis, simulation and timing analysis, and device programming Bag. The software provides EDIF 200 and 3000, LPM, VHDL, Verilog HDL, and other interfaces for additional design entry and simulation support for other industry-standard PC and unix workstation-based EDA tools. The software runs on Windows-based PCs, as well as Sun SPARCstations and HP 9000 Series 700/800 Workstations.