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Features: Throughput: 10 MSPS Signal-to-Noise Ratio: 91.5dB 16-bit No Missing Codes INL: ±0.45 LSBDNL: ±0.35 LSB Power Dissipation: 136mW SAR Architecture in 32-pin LFCSP Package (5mm x 5mm) No Delay/No Pipelining Delay 16-bit resolution, no missing codes Zero error: ± 1LSB Differential Input Range: ± 4.096 V Serial LVDS Interface Self-Clocked Mode Echo Clocked Mode LVDS or CMOS Option Conversion Control (CNV Signal) Reference Option Internal: 4.096 V External ( 1.2 V) Buffered to 4.096 V External: 4.096 V Functional Block Diagram REFINREF VCM1.2V Bandgap IN+IN- Cap DACVIO Logic CNV+, CNV-D+, D–CLK+, CLK-07648-001 ÷ 2 Clock AD7626 SAR String Line LVDSDCO+, DCO- Figure 1. Overview The AD7626 is a 16-bit, 10 MSPS, charge redistribution successive approximation register (SAR) based analog-to-digital converter (ADC). The SAR architecture allows unmatched performance both in noise (91.5dB SNR) and linearity (±0.45 LSB INL). The AD7626 integrates a high speed, 16-bit sampling ADC, an internal conversion clock and an internal buffered reference. On a CNV edge, it samples the voltage difference between the IN+ and IN- pins. The voltages on these two pins swing in opposite phases between 0 V and REF. The 4.096 V reference voltage (REF) can be generated internally or applied externally. All conversion results are available on a single LVDS self-clocked or echo-clocked serial interface, reducing external hardware connections. The AD7626 is available in a 32-lead, five mm x 5 mm LFCSP package with specified operation from -40°C to +85°C. Application Digital Imaging System Digital X-ray Digital MRICCD and Infrared Camera High Speed Data Acquisition High Dynamic Range Receiver Communication Spectrum Analysis Test Equipment

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