Programmable Logic EPF10K100ARC240-3N Flexible Interconnect - FastTrack® Interconnect Continuous Routing Fabric for Fast, Predictable Interconnect Latency - Dedicated Carry Chain for Arithmetic Functions such as Fast Adders, Counters and Comparators (by software tools and Megafunctions automatically used) - Dedicated cascade chain for high-speed, high-fan-in logic functions (automatic use of software tools and megafunctions) - Programmable logic EPF10K100ARC240-3N Tri-state emulation to implement internal tri-state bus - 6 Global clock signal and four global clear signals Robust I/O pins - Individual tri-state outputs per pin enable control of open gutter options on each I/O pin - Programmable output slew rate control to reduce switching noise - FLEX 10 ka devices support hot-socketing Peripheral registration for quick setup and clock-to-output latency Programmable logic EPF10K100ARC240-3N Flexible packaging option, programmable logic EPF10K100ARC240-3N available in a variety of packages 84-600 pins ( See Tables 4 and 5) Compatible with other FLEX 10k-plug devices in the same package - FineLine BGATM package maximizes board space efficiency Software design support and automatic place-and-route provided by Altera Development System Windows-based PC and Sun SPARCstation, HP 9000 series 700/800 workstations Additional design entry and simulation support provided by EDIF 2 0 0 3 00 netlist files, parametric modules (line minutes), library DesignWare components, Verilog HDL , Hardware Description Language (VHDL), and interfaces to other popular EDA tools from manufacturers such as Rhythm, Paradigm Logic, Mentor Graphics, OrCAD, Synopsys, Synplicity VeriBest, Viewlogic

?FLEX 10K and FLEX 10KA device package types include Plastic J-lead Chip Carrier (PLCC), Thin Quad Flat Package (TQFP), Plastic Quad Flat Package (PQFP), Power Quad Flat Package (RQFP), Ball Grid Array (BGA), pin-grid array (PGA) and FineLine BGATM packages. (2) This option supports 256-pin FineLine BGA packages. All FineLine BGA packages are pin compatible by using the same frame footer migration. For example, a board can be designed to support both 256-pin and 484-pin FineLine BGA packages. Altera's FLEX 10K device is the industry's first embedded pld. Based on reconfigurable CMOS SRAM cells, the Flexible Logic Cell Matrix (FLEX) architecture contains all the features required to implement general-purpose gate array functionality. With up to 250,000 gates, the FLEX 10K series provides the density, speed and features to integrate an entire system, including multiple 32-bit buses, into a single device.

The FLEX 10K device is reconfigurable, allowing 100% testing before shipping. Therefore, the designer does not need to generate test vectors for fault coverage purposes. Additionally, designers do not need to manage an inventory of different ASIC designs; the FLEX 10K device can be configured with specific functions on the board.

Table 6 shows the FLEX 10K performance for some common designs. All performance values were obtained using Synopsys design software or LPM functions. Applications do not require special design techniques; designers simply infer or instantiate a function in Verilog HDL, VHDL, Altera Hardware Description Language (AHDL), or a schematic design file.