Programmable Logic EPF10K100EBC356-2X ? Embedded Programmable Logic Device (Device) Programmable Logic EPF10K100EBC356-2X that provides system-on-a-programmable-chip (SOPC) integration in a single device - Programmable Logic EPF10K100EBC356-2X Enhanced Embedded arrays implement megafunctions such as efficient memory and specialized logic functions, dual-port functions up to 16-bit width/Embedded Array Block (EAB) - logic arrays for general logic functions High density - 30,000 to 200,000 typical gates (See Tables 1 and 2) - RAM 98304 bits (4096 bits/EAB), can use all this without reducing logic capability Programmable logic EPF10K100EBC356-2X System Level Features - MultiVoltTM driver or I/O pins can be driven by 2.5 V , 3.3V, or 5.0-V - Low-Power Devices Bidirectional I/O Performance (tSU and tCO) 212 MHz,

• The Altera FLEX 10KE device is an enhanced version of the FLEX 10K device. The FLEX architecture is based on reconfigurable CMOS SRAM elements that integrate all the functions needed to implement general-purpose gate array functionality. With up to 200,000 typical gates, the FLEX 10KE provides the density, speed and features to integrate an entire system (including multiple 32-bit buses) into one device.

The ability to reconfigure the FLEX 10KE device allows 100% testing before shipping and allows designers to focus on simulation and design verification. FLEX 10KE reconfigurability eliminates inventory management and fault coverage test vector generation for gate array designs.

Table 5 shows the FLEX 10KE performance for some common designs. All performance values were obtained using Synopsys design software or LPM functions. No special design techniques are required to implement an application; designers simply infer or instantiate a function in Verilog HDL, VHDL, Altera Hardware Description Language (AHDL), or a schematic design file.

On all FLEX 10KE devices (except the EPF10K50E and EPF10K200E devices), the input path from the I/O pad to the FastTrack interconnect has a programmable delay element that can be used to guarantee zero hold time. This feature is also supported on EPF10K50S and EPF10K200S devices. Depending on where the IOE is relative to where it is being driven, the designer can choose to turn on the programmable delay to ensure zero latency, or turn it off to minimize setup time. This feature is used to reduce setup time for complex pin-to-register paths such as PCI designs.