?Programmable Logic EPF10K130EFC484-1N Embedded Programmable Logic Device (Device) that provides system-on-a-programmable-chip (SOPC) integration in a single device-enhanced embedded array implementing megafunctions such as efficient memory and specialized logic functions , Dual port functions up to 16-bit width/Embedded Array Block (EAB) - Program Logic EPF10K130EFC484-1N Logic Array General Logic Function High Density - 30,000 to 200,000 typical gates (see Tables 1 and 2) - 98304 bits of RAM (4096 bits/EAB), programming logic EPF10K130EFC484-1N can use all of these without reducing logic capability System level features - MultiVoltTM drivers or I/O pins can be driven by 2.5v, 3.3v, or 5.0-v- Low-power device bidirectional I/O performance (tSU and tCO) 212 MHz, programming logic EPF10K130EFC484-1N Fully compliant with PCI Special Interest Group (a bus standards body) PCI Local Bus Specification, Version 2.2 3.3-V operating speed 33 MHz or 66 MHz - Class 1 Device Compliant with PCI Local Bus Specification, Version 2.2 for 5.0-V Operation - Built-in Joint Test Action Group (JTAG) Boundary Scan Test (BST) circuitry compliant with IEEE Std. 1149.1-1990, no additional device logic required ? - Manufactured with an advanced process and operating software Internal supply voltage 2.5V - Reconfigurability (ICR) via external configuration device, smart controller, or JTAG port - ClockLockTM and ClockBoostTM options to reduce latency/slope and clock multiplication - Built-in low-skew clock distribution tree - 100% functional testing of all devices; no test vectors or scan chains required, pull-up before and during I/O pin configuration Flexible interconnect - FastTrack® interconnect continuous routing structure for fast, Predictable interconnect latency - dedicated to functions such as arithmetic Fast carry chain snakes, counters and comparators (automatic use of software tools and megafunctions) Dedicated cascaded chain to implement high-speed, high-fan-in logic functions (automatic use of software Tools and megafunctions) - Tri-state emulation implements internal tri-state bus - 6 global clock signals and four global clear signals Robust I/O pins - individual tri-state outputs per pin enable control of open drain options on each I /O pin - Programmable output slew rate control reduces switching noise clipping to V CCIO on a pin-by-pin basis, supports hot-socketing