Features

Support the reliable operation of DLP4500 DMD

two types of input interfaces

- yuv, YCRCB or RGB data format format

-Each color 8, 9 or 10 digits

-Pixel clock supports up to 150 MHz

-Sofou, LVDS tablet display (FPD-Link) compatible input interface

- Signal source supports the four -type disciplinary pixel mapping mode of 8, 9, 10 YUV, YCRCB or RGB format input sources up to 90 MHz effective pixel clock rates

123] Two operation mode

- Structural light mode

-The pixel accurate mode, no video processing

-Enter input data to one -to -one one -to -one microscope to microscope Map

-The 1 -bit binary mode rate of 4225 Hertz

─ 8 -bit gray mode rate up to 120 Hz

- Video projection mode

- Programmable color coordinates adjustment

- programmable color space conversion

- programmable off -exhale

- time and space reuse (jitter)

#8226 Dynamic and deformation zoom

Support flash screen display

support the frame rate of 10 Hz to 120 Hz

Dual data rate DMD interface

microprocessor peripheral equipment

- programmable PWM and capture timer

- Two I2C ports

] - A USB 1.1 port

-32 KB's internal RAM

- Dedicated LED PWM generator

Integrated clock generation circuit

] - Work on a single 32 MHz crystal

- Integrated expansion clock

- Micro -processor parallel flash memory

System control:

] - Integrated DMD power supply and resetting driver control

-DMD level and vertical image flip

JTAG boundary scanning test support

419; 419; 419 Plastic ball grid package

Application

Machine vision

Industrial test

3D scan

3D optical signess

Automatic fingerprint recognition

] Human face recognition

augmented reality

Interactive display

Information overlay

] spectroscopy

Chemical analyzer

Virtual instrument

Instructions

DLPC350

Digital controller is part of the DLP 0.45 WXGA chipset, supporting the reliable operation of DLP4500 DMD or digital microscope equipment. The DLPC350 controller provides a convenient and multi -function interface between the user's electronic device and DMD, supports high -speed mode rates, and provides LED control and data formatting for multiple input resolution. The DLPC350 also outputs a trigger signal to synchronize the mode with the camera, sensor or other peripheral devices.

DLPC350 controller can integrate DLP 0.45 WXGA chip components into small -size and low -cost light to applications. The application instance of the 0.45 WXGA chipset includes a three -dimensional scanning or metering system with structural light, interactive display, chemical analyzer, medical instrument, and other terminal equipment that requires spatial light adjustment (light steering and graphical).

DLPC350 is one of the two devices in the 0.45 WXGA chipset (see Figure 1). Another device is DLP4500 DMD.

block diagram

In a DLP -based solution, the image data of the image data from the DLPC350 input port to DMD is 100%numbers. The image keeps the digital form and does not convert it to analog signal. DLPC350 processing digital input image and converting the data to the format required for DLP4500. DLP4500 controls the light by using binary pulse width (PWM) for each microscope.

FIG. 2 is the function box diagram of DLPC350. As part of the pixel processing function, the DLPC350 provides format conversion function: color interpolation and color space conversion. The DLPC350 also provides a variety of image enhancement functions. The DLPC350 also supports the necessary function of formatting the input data to DMD. Pixel processing function allows DLPC350 and DLP4500 to support multiple resolution, including NTSC, PAL, XGA and WXGA. The pixel processing function can selectively bypass the 912 × 1140 pixel resolution of this machine to support direct one -to -one pixel mapping.

When the accurate pattern is required, the 912 x 1140 input resolution pattern is related to the corresponding microscope on the DLP4500. DLPC350 supports high -speed display of these patterns. This function is very suitable for technologies such as structural light, additive manufacturing or digital exposure.

The command can be input to DLPC350 via the I2C interface.

DLPC350 receives 24, 27 or 30 RGB data as input with a frame rate of up to 120 Hz. This frame rate consists of three colors (red, green, and blue), and each color is evenly allocated in the 120Hz frame rate. Therefore, each color is assigned a time clearance of 2.78ms. Because each color has 8, 9 or 10 depths, each color slot is further divided into bit plane. The position plane is a two -dimensional arrangement extracted from all pixels of the full color 2D image to achieve dynamic depth. See Figure 3.

The length of each plane in the time slot is weighted by the corresponding power represented by its binary. This provides the binary pulse width of the image. For example, 24 -bit RGB input has three colors, and the depth of each color is 8 bits. Each color time clearance is divided into 8 bit planes, and the weight of all planes in this time slot is equal to 256. As shown in Figure 4, please refer to Figure 4 to understand the division in the frame.

Therefore, a single video frame consists of a series of plane. Because the DMD image can be opened or closed, it can create images by opening the image corresponding to the bit phase. Under the modulation of the binary pulse width, the amount of the color is reappeared by the time to control the reflector. For 24 -bit RGB frames entered into DLPC350, DLPC350 creates 24 -bit planes, stores it in the dual buffer EDRAM embedded in the chip, and sends it to DLP4500 DMD for one -bit plane at a time. Depending on the bit plane, the DLPC350 controls the time when the plane is illuminated, and the strength of the plane is controlled. In order to improve the image quality in the video frame, the DLPC350 uses the space -time algorithm to mix and interweave these planes, slots and color frames.

Structural Light Application

For other applications that do not need this video enhancement, you can bypass the video processing algorithm and replace it with a set of specific planes. The depth of the mode is then distributed into the corresponding time slot. In addition, the output trigger signal also synchronizes when the time clearance is synchronized to indicate when the image is displayed. For structural light applications, this mechanism provides a set of patterns and sends signals to the camera to capture these patterns covering these patterns.can.

DLPC350 stores two 24 -bit frames in its internal memory buffer. This 48 -bit plane display buffer allows DLPC350 to send a 24 -bit buffer to the DMD array, while the second buffer is filled by flash or input through 24 -bit RGB interface. In the current mode, the DMD array shows the previous 24 -bit frame, while the current frame fills the second 24 -bit frame of the buffer. Once a 24 -bit frame is displayed, the buffer will rotate to access the next 24 -bit frame to DMD. Therefore, the displayed image is the 24 -bit frame behind the data transmitted by the 24 -bit RGB parallel interface.

In the structure of the structure, 48 -bit planes can be pre -installed from the flash, and then sorted with a pattern of different bits. In order to synchronize the camera and the displayed pattern, the DLPC350 supports three triggers: Mode 0, Mode 1 and Mode 2.

In Mode 0, vertical synchronization is used as trigger input. In Mode 1, No. 1 trigger pulse indicator DLPC350 enters the next mode, and No. 2 triggers start and stop mode sequence. In mode 0 and mode 1, the exposure time of the Trig_out_1 frame mode, while Trig_u 2 represents the beginning of the mode sequence or the internal buffer boundary of the 24 -bit plane. In Mode 2, the trigger 1 signal is switched between two continuous modes, and the trigger pulse enters the next pair of mode. In the trigger mode 0, as shown in Figure 5, the vsync start -up mode sequence is displayed. The pattern sequence consists of three continuous patterns. The first mode sequence consists of P1, P2 and P3. Because P3 is a RGB mode, it is shown in the sequence of P3.1, P3.2 and P3.3. The second mode sequence consists of three modes: P4, P5 and P6. The third sequence includes P7, P8, and P9. The TRIG_OUT_1 box shows each mode, and trig_out_2 represents the beginning of each mode in the three mode sequences. The example of the trigger mode 1 is shown in Figure 6. Display four pattern sequences. The trig_out_1 box shows each mode, and trig_out_2 represents the beginning of each four mode sequences. Trigger pulse propulsion mode. Another example of

Mode 1 is shown in Figure 7, which shows three mode sequences. The trig_out_1 box shows each displayed pattern, trig_out_2 represents the beginning of each three pattern sequences. _2 trig_ is used as a startup/stop signal. At high, the pattern sequence begins or continues. Please note that in the middle of the P4 mode, the trig_ in _2 is low, so the sequence stops display P4. When triggering trig_, the pattern sequence continues at the stop and re -display the P4.

For trigger mode 2, as shown in Figure 8, Trig-IN-1 alternate between two modes, and Trig-IN_-IN-2 advancesA pair. Table 1 shows the allowable mode combination related to the depth of the pattern.

Typical system application

Use the typical embedded system application of DLPC350 Essence In this configuration, the DLPC350 controller supports 24 -bit parallel RGB input from the external source or processor (typical input of the LCD interface). The system also supports static and dynamic video sources. However, the controller only supports cyclical synchronization pulse sources. This is the ideal choice of sports video source, but it can also be used for static images to maintain cyclical synchronization and only send new data frames when needed. Static images must be completely included in a video frame and meet the time -time constraints. The DLPC350 refreshed the image displayed at the source frame rate, and repeated the previous activity frame within the interval without receiving the new frame.

Related files

Device naming method

Figure 10 provides a legend for it for it for for a legend for it for for it for for it for for a legend for it. Read the complete device name of any DLP device.

Device logo

The device is marked consisting of fields shown in Figure 11.

System power power -powered and reset

There are several factors related to system power and reset, which will affect the DC 350 power pins of the DLPC350 power pins (offset) and and and and and and and and and. Communicate noise.

Conditions for breach

DLPC350 executes power -to -power initialization routine during the system. This program will make the controller default Reset will be released. Most other clocks will default to ""disable"