Embedded Processor and Controller MPC875ZT133 is a multi-function single-chip integrated microprocessor and peripheral combination that can be used in various controller applications, communication and networking systems. Embedded processor and controller MPC875ZT133 provides more powerful ATM functions than other ATM-capable members of the MPC860 family

Embedded processor and controller MPC875ZT133 consists of three modules, each module uses 32-bit internal bus: embedded processor and controller MPC875ZT133 core, system integration unit (SIU) and communication processor module (CPM).

The following list summarizes the main features of the embedded processor and controller MPC875ZT133: ? Embedded MPC8xx core 133 MHz ? Maximum frequency for external bus operation is 80 MHz (1:1 mode) - 133-MHz core frequency only supports 2:1 Modes - 66/80-MHz core frequency supports 1:1 and 2:1 modes? Issue, 32-bit core (compatible with Power Architecture Definition) and 32 32-bit General Purpose Registers (GPRs) - The core performs branch prediction conditional prefetch and Unconditional execution 8-Kbyte data cache and 8-Kbyte instruction cache (see Table 1) - instruction cache is bidirectional, set-associative 256 sets in 2 blocks, data cache is bidirectional, 256 sets set-associative - cache instruction and The data cache is maintained in 128-bit (4-word) cache blocks - the cache is physically solved, implementing a least recently used (LRU) replacement algorithm, and based on a lockable cache block, MMUs support 32 TLBs, all Associated instruction and data TLBs - MMUs support multiple page sizes of 4, 16, 512 Kbytes and 8 Mbytes; 16 virtual address spaces and 16 protection groups - Advanced on-chip emulated debug mode? Up to 32-bit data bus (dynamic bus size 32-bit address lines for 8, 16 and 32 bits? Memory controller (8 banks), including full dynamic random access memory (DRAM) chip controller - each bank can be selected or RAS supports DRAM bank - 30 Wait-State Programmable / DRAM Memory Banks - Glueless Interface, Sims, SRAM, eprom, Flash eprom, and other memory devices - DRAM Controller Programmable to support most sizes and speeds Memory Interface - CAS Quad Line , four rows, one row OE - Boot chip select available at reset (8-bit, 16-bit or 32-bit memory options) - Variable block size (32 Kbytes - 256 Mbytes) - Optional write protection - On-chip bus arbitration logic - General purpose timers - 4 x 16-bit timers or 2 x 32-bit timers - Gate mode can enable/disable counting - Interrupts can be masked on reference match and event capture? Two Fast Ethernet Controllers (FEC) Two 10/ 100 Mbps Ethernet/IEEE Std 802.3? CDMA/CS. Embedded Processor and Controller MPC875ZT133 This interface is controlled by MII and/or RMII? System Integration Interface Unit (SIU) - Bus Monitor Software Supervision Periodic Interrupt Timer (PIT) - Clock Synthesizer Decrement and Time Base - Reset Control The server security engine is optimized to handle all algorithms related to IPsec, SSL/TLS, SRTP, IEEE 802.11i™ standards and iSCSI processing. Available on the MPC875, the security engine consists of a cryptographic channel, a controller, and a set of cryptographic hardware accelerators (CHAs). CHAs are: - Data Encryption Standard Implementation Unit (DEU) - DES, 3DES - Two keys