The programmable logic XC3S1400A-4FTG256I programs Spartan-3A FPGAs by loading configuration data into robust, reprogrammable static CMOS configuration latches (CCLs) that collectively control all functional elements and routing resources. The FPGA's configuration data is stored in an external PROM or some other non-volatile medium, either on-board or off-board. After power-up, the programmable logic XC3S1400A-4FTG256I writes configuration data to the FPGA using any of seven different modes: ? Master from Xilinx Serial Flash Platform ? Serial Peripheral Interface (SPI) from an industry standard SPI serial Flash™ Byte Peripheral Interface (BPI) from an industry standard hybrid or x8/x16 parallel and Flash™ slave serial, usually from a processor? Download slave parallel, usually from a processor? Boundary scan download (JTAG ), typically downloaded from a processor or system for testing. Additionally, the Spartan-3A FPGA supports MultiBoot configuration, allowing two or more FPGA configuration bitstreams to be stored in one SPI serial flash or one BPI parallel or flash. The programmable logic XC3S1400A-4FTG256I FPGA application controls which configuration is loaded next and when. Programmable Logic XC3S1400A-4FTG256I In addition, each Spartan-3A FPGA contains a unique factory-programmed device DNA identifier for tracking purposes, anti-cloning design, or IP protection.

The FPGA select interface supports many popular single-ended and differential standards. Table 2 shows the number of user I/Os and the number of differential I/O pairs available for each device/package combination. Some user I/Os are unidirectional input-only pins, as shown in Table 2. The Spartan-3A fpga supports the following single-ended standards: ? 3.3 v Low Voltage TTL (LVTTL) ? Low Voltage CMOS (LVCMOS) at 3.3 v, 2.5 v, 1.8 v, 1.5 v, 3.3 or 1.2 v? v PCI 33 MHz or 66 MHz ?HSTL I, II, III at 1.5v and 1.8v, commonly used in memory applications? Surrey I and II at 1.8v, 2.5v and 3.3v, commonly used in memory applications Spartan-3A fpga supports the following differential standards: , mini-LVDS, RSDS, PPDS I/O LVDS I/O at 2.5V or 3.3V Bus LVDS I/O at 2.5V or 3.3V TMDS I/O at 3.3V Differential HSTL and SSTL at 3.3V LVPECL input for I/O at 2.5V or 3.3V