Programmable Logic XC2VP20-6FF1152I?Programmable Receiver Equalization? Internal AC Coupling? On-Chip 50??Termination Eliminates Need external termination resistors? Pre- and Post-Driver Serial and Parallel TX-to-RX

Programmable logic XC2VP20-6FF1152I Internal loopback mode to test operability? Programmable comma detection - allows any protocol - allows detection of any 10-bit character?

RocketIO transceiver capabilities (except XC2VPX20 and XC2VPX70)? Full duplex serial transceivers (parallel converters) with baud rates from 600 Mb/s to 3.125 Gb/s? 100 Gb/s duplex data rates (20 channels)? Overall Clock Synthesis and Clock Recovery (CDR) Fibre Channel, 10G Fibre Channel, Gigabit Ethernet, 10 Gb Accessory Unit Interface (XAUI) and Infiniband-Compliant Receivers? 8-16, or Programmable Logic XC2VP20-6FF1152I 32-bit Selectable Internal FPGA Interface ? 8 B/10B Encoder and Decoder (optional) ? 50 ? /75? On-chip Selectable Transmit and Receive Terminations ? Programmable Comma Detection ? Channel Bonding Support (from 2 to 20 Channels) ? Rate Matching via Insertion/Deletion Characters ? Selectable Pre-Emphasis of Four Levels ? Output Differential Voltage of Five Levels ? Per-Channel Internal Loopback Modes ? 2.5 V Transceiver Supply Voltage

PowerPC RISC processor block features (except XC2VP2)? Embedded 300+ MHz Harvard architecture block? Low power consumption: 0.9 mW/MHz? Set-Associative Instruction Cache? 16 KB Bidirectional Set-Associative Data Cache? Memory Management Unit (MMU) - 64-entry Unified Translation Lookaside Buffer (TLB) - Variable page size (1 KB 16 MB)? Dedicated chip-level memory ( OCM) interface? Support for IBM CoreConnect? Bus architecture?? Timer facility debug and trace support

Virtex-II Career Platform FPGA Technology (all devices)? SelectRAM + Memory Hierarchy - 8 Mb of True Dual Port RAM 18 Kb Block SelectRAM + Resources - 1378 Kb of Distributed SelectRAM + Resources - High Performance External Memory? Arithmetic Function Interface - Dedicated 18-bit x 18-bit multiplier module for fast look-ahead carry logic chain? Flexible logic resources - 88192 internal register/clock enable latch - 88192 (nearby area) or cascadable lookup table variable (1 to 16 bits) Shift Registers - Wide Multiplexer and Wide Input Function Support - Horizontal Cascade Chain and Product Sum Support