Programmable Logic XC3S1400A-4FGG676C ? Spartan ?-3A Series Field Programmable Gate Arrays (FPGAs) Solve Most Design Challenges of High Volume, Cost Sensitive, I/O Intensive Electronics Programmable Logic XC3S1400A-4FGG676C

application. Programmable Logic XC3S1400A-4FGG676C The population density of this family of five varies widely from 50,000 system gates to 1.4 million system gates, as shown in Table 1. SPARTAN-3aFPGAs are part of the extended SPARTAN-3a family, which also includes the non-volatile SPARTAN-3an and higher density SPARTAN-3a DSPfpga. The Programmable Logic XC3S1400A-4FGG676C Bada 3a family builds on the success of the earlier Spartan-3E and Spartan-3 FPGA families.

The programmable logic XC3S1400A-4FGG676C features improved system performance and reduced cost of configuration. Programmable logic XC3S1400A-4FGG676C These enhancements to the Spartan 3a family, combined with proven 90nm process technology, deliver

More features and bandwidth per dollar than ever before, setting a new standard for the programmable logic industry. Because of their very low cost, are Spartan 3a FPGAs suitable for a wide range of consumer electronics applications including broadband access, home networking,

Display/projection and digital television equipment. The Spartan 3a series is a better option for mask programming asic. FPGAs avoid high initial costs,

? 640+ Mb/s data rate/I/O? LVDS differential, standard deviation, mini-LVDS, HSTL/Surrey differential I/O integrated differential termination resistors? Enhanced double data rate (DDR) support? DDR/ DDR2 SDRAM supports up to 400 Mb/s? Fully compatible with 32-bit/64-bit, 33/66 MHz PCI? Technical support? Rich, flexible logic resources? Density 25344 logic cells, including optional shift register or distributed memory Support? Efficient broad multiplexer, wide logic? Fast predictability carry logic? Enhanced 18 x 18 multiplier with optional pipeline? Comes with fast block RAM and byte writes to enable processor applications? 176 to provide efficient distributed RAM? 8 Digital Clock Managers (DCMs)? Clock Phase Difference Elimination (Delay Locked Loop)? Frequency Synthesis, Multiplication, 8 A low-skew global clock network with an additional 8 clocks per half device, plus a wealth of low-skew routing configuration interfaces to industry standard PROMs. Space Saving SPI Serial Flash PROM × × 8 or x8/x16 BPI Parallel NOR Flash PROM ? Low-cost Xilinx? Platform Flash and JTAG ? Unique Device DNA Logo Design Certification? Load Multiple Bitstreams FPGA Control? Post-configuration CRC Check? Complete Xilinx ISE? WebPACK? Development system software support + Spartan-3A Starter Kit? MicroBlaze? and PicoBlaze? Embedded processors? Low-cost QFP and BGA packaging, no pb options? Common footprint support for easy density migration? Compatible Select Spartan-3AN non-volatile FPGAs? Compatible with higher density Spartan-3A DSP FPGAs? XA automotive version available