Programmable logic device LC4256V-75TN176E? Features? Programmable logic device LC4256V-75TN176EHigh Performance ?fMAX = 400 MHz Maximum operating frequency?tPD = 2.5 ns Propagation programmable logic device LC4256V-75TN176E delay? Up Four global clock pins with programmable Clock Polarity Control? Up 80 PTs per output? Ease Design? Macrocell of programmable logic device LC4256V-75TN176EEnhanced with individual clock, reset, preset and clock enable control? Programmable logic device LC4256V-75TN176E Up Four global OE controls ? Individual local OE controls per I/O pin ? Excellent First-Time-FitTM and retrofit ? Fast path, SpeedLockingTM Path, and ? Wide wide-PT path input control (36 input logic blocks) Fast counters, state machine and address decoder ? Zero Power (ispMACH 4000 Z) Low Power (ispMACH 4000 V/B/C) ? Typical quiescent current 10 μA (4032Z) ? Typical quiescent current 1.3 mA (4000C) ? 1.8 core low dynamic power? ispMACH 4000 VZ operation down to 1.6V VCC

? Broad Device Offering ? Supported in Multiple Temperature Ranges – Commercial: 0 to 90 °C Junction (Tj) – Industrial: –40 105 °C Junction (Tj) – Extended: –40 130 °C Junction (Tj) ? For AEC- Q100 Compatible devices, refer to LA-ispMACH 4000 V/Z Automotive Data Sheet ? Easy System Integration ? Superior Solution for Power Sensitive Consumer Applications? Operation 1.8 3.3 2.5 V, V or V LVCMOS I/O ? Operation 3.3 V (4000V) , 2.5 V (4000B) or 1.8 V (4000C/Z) supply? 5 V tolerant I/O LVCMOS 3.3, LVTTL, and PCI interface? Hot-socketing? Open-drain capability? Input pull-up, using IEEE 1532 compatible interface 3.3 V/2.5 V/1.8 V in-system programmable (ISP?

The high-performance ispMACH 4000 series provides an ultra-high-speed CPLD solution. The series mixes two of the most popular architectures: ispLSI? 2000 and ispMACH 4A. The ispMACH 4000 architecture retains the advantages of both families, focusing on major innovations, combining high performance and low power consumption in one flexible CPLD family.

The ispMACH 4000 combines high speed, low power consumption and the flexibility required for ease of design. With its robust global routing pool and outgoing routing pool, this family provides excellent first-time match, timing predictability, routing, pin-out retention, and density migration.

The ispMACH 4000 series products range in densities from 32 to 512 macrocells. There are various densities of i/O combinations in thin quad flat pack (TQFP), chip scale BGA (csBGA) and fine pitch thin BGA (ftBGA) packages from 44 to 256 pins/ball. Table 1 shows the macrocell, package, and I/O options, as well as other key parameters.