Programmable logic LFE3-70EA-6FN1156C Higher logic density for increased system integration? 17k to 149k near area? 116-586 I/Os embedded parallel converter? 150 Mbps for general purpose 8b10b 3.2 Gbps, 10-bit parallel conversion Adapter, and 8-bit parallel converter modes? Programmable logic LFE3-70EA-6FN1156C Data rate 230 Mbps for all other protocols 3.2 Gbps per channel? 16 channels/device: PCI Express, SONET/SDH Ethernet (to 1gbe, SGMII XAUI), CPRI, SMPTE 3g and Serial RapidIO sysDSP??Fully cascadable chip structure?12 to 160 chip high performance multiply, accumulate?Powerful 54-bit ALU operation?Time division multiplexing MAC sharing?Programmable logic LFE3- 70EA-6FN1156C Rounding and truncation? Each slice supports half 36x36, two 18x18 or quad 9x9 multipliers Advanced 18x36 MAC and 18x18 Multiply-Multiply-Accumulate (MMAC) operations Flexible memory resources? 6.85 mbit sysMEM • Programmable logic LFE3-70EA-6FN1156C Embedded Block RAM (EBR) • 36k to 303k-bit distributed RAM sysCLOCK analog PLL and dlls DDR registers in the I/O cell

Dedicated read/write leveling function (ISI) Corrected Output Programmable sysI/O? Buffer Supports Extensive Interface Chip Termination?? Selectable Equalization Filter Input? LVTTL and LVCMOS 33/25/18/15/12? Surrey 33/25/18/ 15i, II? HSTL15i and HSTL18i, II? PCI and differential HSTL, Surrey? LVDS, Bus-LVDS, LVPECL, rsd, MLVDS Flexible device configuration? Dedicated bank configuration I/O? SPI boot flash interface support ? Slave SPI?? Dual Image TransFR? I/O for simple field updates? Soft error detection Embedded macro system level support? for initialization & general? 1.2 V power core

The Lattice eecp3™ (Economy + 3rd Generation) family of FPGA devices is optimized to provide high-performance features such as enhanced DSP architecture, high-speed SERDES, and high-speed source-synchronous interfaces in an economical FPGA fabric. This combination is achieved through advanced device architecture and the use of 65nm technology, which makes these devices suitable for high-volume, high-speed, low-cost applications.

The gridticeecp3 device family expands the look-up table (LUT) capacity to 149K logical elements and supports up to 586 user I/Os. The Lattice eecp3 device family also offers up to 320 18x18 multipliers and a wide range of parallel I/O standards.

The grid eecp3 FPGA structure is optimized for high performance and low cost. LatticeECP3 devices utilize reconfigurable SRAM logic technology, offering popular building blocks such as LTB-based logic, distributed and embedded memory, phase-locked loops (PLLs), delay-locked loops (DLLs), pre-engineered source-synchronous I /O support, enhanced sysDSP slices, and advanced configuration support, including encryption and dual-boot capabilities.