?Digital signal processor ADSP-BF524BBCZ-3A features 600 mhz processor high-performance blackfish two 16-bit macs, two 40-bit alu family, four 8-bit video processors, 40-bit shifter RISC- The like register and instruction model is easy to program and compiler-friendly supports advanced debugging, tracing, performance monitoring accepting a wide range of supply voltages for internal and I/O operations. Digitizer Processor ADSP-BF524BBCZ-3A See page 28 Programmable On-Chip Voltage Regulator Specification for Automotive Applications (ADSP-BF523/ADSP-BF525/ADSP-BF527 processors only). Digitizer Processor ADSP-BF524BBCZ-3A See Automotive Products in 289-Ball-Ball and 208-CSP_BGA Package Memory 132 kbytes of on-chip memory (see Table 1 for Page3 L1 and L3 memory size details) Digitizer Processor ADSP-BF524BBCZ-3A External memory controller with glueless SDRAM and asynchronous support for 8-bit and 16-bit memory Flexible boot options from external flash, SPI, and digitizer Processor ADSP-BF524BBCZ-3A Twin memory or from host device included SPI, Twin, and UART Code Security Lock Box Security Technology One Time Programmable (OTP) Memory Management Unit provides memory protection

Peripherals USB 2.0 high-speed on-go (OTG) integrated PHY IEEE 802.3 compliant 10/100 Ethernet MAC Parallel Peripheral Interface (PPI), supports ITU-R 656 video data format Host DMA port (HOSTDP) 2 dual channel, full duplex Synchronous Serial Ports (SPORTs) supporting 8 stereo I2S channels 12 peripheral DMAs, 2 master Ethernet MAC 2 memory-to-memory for input Serial Peripheral Interface (SPI) compatible with external request lines and 54 interrupt event handlers Port 2 UART transmit support 2-wire interface (twin) Eight 32-bit timer/counter with PWM controller Support 32-bit up/down counter rotation Support real-time clock (RTC) and watchdog timer 32-bit core timer 48 General purpose I/Os (GPIOs) with programmable hysteresis NAND flash controller (NFC) debug/JTAG interface PLL on chip with frequency multiplier

When using HWAIT, the host must check ALLOW_CONFIG at least once before starting to configure the host DMA port. After completing the configuration, the host is required to poll the ready bit in HOST_STATUS before starting to transmit data. When the host sends a HIRQ control command, the boot kernel issues a call instruction to address 0xFFA0 0000. It is the responsibility of the host to ensure that valid code is placed at this address. The routine at 0xFFA0 0000 can be a simple initialization routine that configures internal resources, such as the SDRAM controller, and then returns using the RTS instruction. This routine may also be done by the final application, which never returns to the boot kernel. • Boot from 8-bit host DMA (BMODE=0xF) - In this mode, the host DMA port is configured in 8-bit interrupt mode with little endian data formatting. Unlike other modes, the host is responsible for interpreting the boot flow. It writes blocks of data individually to the host DMA port. Before configuring the DMA settings for each block, the host can poll the ALLOW_CONFIG bit in HOST_STATUS, or wait for the HWAIT signal to interrupt. When using HWAIT, the host must check at least ALLOW_CONFIG before starting to configure the host DMA port