The processor controller MCIMX502CVK8B supports standard LCD displays and electrophoretic displays (electronic paper). The processor controller MCIMX502CVK8B display subsystem consists of the following modules: Electrophoretic Display Controller (EPDC) (i. EPDC is a feature-rich, low-power, high-performance direct-drive active-matrix EPD controller. It is specially designed for It is designed to drive E-INKTM EPD panel and supports multiple TFT architecture processor controller MCIMX502CVK8B. The goal of EPDC is to provide an efficient SoC integration function for electronic paper applications, allowing to achieve higher performance levels and lower Power consumption while saving significant bill of materials cost over external solutions. The processor controller MCIMX502CVK8B EPDC module is defined in the context of an optimized hardware/software partition and works with ePXP (see Section 1.1.4 "Graphics Accelerators" ”). The eLCDIF is a high-performance LCD controller interface that supports a rich mode set and allows interoperability with various LCD panels, including DOTCK/RGB and smart panels. The module also supports synchronous operation with ePXP, Allows processed frames to be passed from the ePXP to the eLCDIF through the on-chip SRAM buffer. The eLCDIF can support up to 32-bit interfaces.

Max AHB Crossbar (133 MHz) - Connects the various AHB bus sub-segments in the system and provides decoding into the following slaves:- IP-Bus 1 (66 MHz) - The bus segment contains the core and peripherals accessible to the arm without DMA Capability - IP-Bus 2 (66 MHz) - The bus segment contains the core and peripherals accessible to the arm No DMA Capability - APBH DMA Bridge (133 MHz) - The APBH DMA Bridge is the largest master in terms of memory DMA operations . The APBH bus is an AMBA APB slave bus that provides peripheral access to many high-speed IP blocks on the i.MX50. ?IP-Bus 3 (66mhz) - This third peripheral bus segment contains peripherals accessible by the ARM core and SDMA, as well as DMA capable peripherals. ARM CPUs can access IP-Bus 3 via IP-Bus 1 and SPBA. • Quality of Service Controller (QoSC) - Provides soft and dynamic arbitration/priority control. QoSC works with key display modules such as eLCDIF and EPDC to provide dynamic priority control based on real-time metrics.

I. The MX50 uses dedicated hardware accelerators to achieve state-of-the-art multimedia performance. The use of hardware accelerators provides high performance and low power consumption while freeing up CPU cores for other tasks.

I. The MX50 integrates the following hardware accelerators: GPU2Dv1-2D graphics accelerator, OpenVG 1.1, 200 Mpix/s performance

I. The MX50 includes the following interfaces to external devices

The MX50 application processor is a multimedia-focused product that provides high-performance processing optimized for the lowest power consumption. I. The MX50 processor is Freescale's energy-saving solution product. The MX50 is optimized for portable multimedia applications and features Freescale's advanced ARM Cortex-A8™ core implementation running at speeds up to 1GHz. I. The MX50 offers a powerful display architecture including a 2D Graphics Processing Unit (GPU) and Pixel Processing Pipeline (ePXP). Also, me. The MX50 includes a complete integrated electrophoretic display function. I. The MX50 supports DDR2, LPDDR2 and LPDDR1 DRAM at clock rates up to 266mhz, enabling a range of performance and power tradeoffs.