Programmable logic XC2S100-5FG256C ? Spartan-II series FPGAs have a regular, flexible, programmable configurable logic block (clb) architecture, surrounded by a series of programmable input/output blocks (IOBs). There are four delay lock loops (DLLs), one in each corner of the die. The two columns of block RAM are located on opposite sides of the die, between the clb column and the IOB column. These functional elements are interconnected through a powerful, generic routing channel hierarchy (see Figure 1). Programmable logic XC2S100-5FG256C

Spartan-II FPGAs can be customized by loading configuration data into internal static memory cells. This approach enables infinite reprogramming cycles. The values stored in these cells determine the logic functions and interconnects implemented in the FPGA. Configuration data can be read from external serial PROM (master)

serial mode), or writing to the FPGA in slave serial, slave parallel, or boundary scan mode. Programmable logic XC2S100-5FG256C

Programmable logic XC2S100-5FG256C Spartan-II FPGAs are typically used in high-volume applications where the versatility of a fast programmable solution adds an advantage. Spartan-II FPGAs are ideal for shortening product development cycles while providing a cost-effective solution for high-volume production.

Spartan-II FPGAs enable high-performance, low-cost operation through advanced architecture and semiconductor technology. Spartan-II devices provide system clock rates up to 200mhz. In addition to the advantages of traditional high-density programmable logic solutions, Spartan-II FPGAs offer on-chip synchronous single-port and dual-port RAM (block and distributed forms), DLL clock drivers, programmable sets and resets for all flip-flops , fast carry logic, and many other features.

The Spartan®-II Field Programmable Gate Array, shown in Figure 2, consists of five main configurable elements:

?IOBs provide interface between package pins and internal logic ?clbs provide functional elements to construct most logic ?4096-bit dedicated block RAM memory per clock dll ?Clock distribution delay compensation and clock domain control ?Multipurpose multilevel interconnect structure

As shown in Figure 2, the CLBs form the central logical structure with easy access to all support and routing structures. IOBs are in all logical sums

Memory components that easily and quickly route signals on and off the chip.

Programmable Logic XC2S100-5FG256C Values stored in static memory cells control all configurable logic elements and interconnect resources. These values are loaded into the memory unit at startup and can be reloaded if the device's functionality needs to be changed. The following sections discuss these elements in detail. input/output block

As shown in Figure 2, the Spartan-II FPGA IOB has input and output features that support multiple I/O signaling standards. These high-speed inputs and outputs are capable of supporting state-of-the-art memory and bus interfaces in various states. Table 3 lists several supported standards, along with the reference, output, and termination voltages required to meet the standards. In master serial mode, the FPGA's CCLK output drives a Xilinx PROM that provides a serial stream of configuration data to the FPGA's DIN input.