The static random access memory N02L6181AB27I is an integrated memory device containing a 2 Mbit static random access memory arranged in 16 bits for 131,072 words. The device is designed and manufactured using the semiconductor company's advanced CMOS technology to provide high-speed performance and ultra-low power consumption. The basic design is the same as Semiconductor's N02L63W3A, which handles higher voltages. The device features single-chip enable (CE) control and output enable (OE) for easy memory expansion. Byte controls (UB and LB) allow independent access to the upper and lower bytes. ?Static random access memory N02L6181AB27I is the best choice for a variety of low-power applications, such as battery backup and handheld devices. The device can operate over a very wide temperature range of -40°C to +85°C and is available in a JEDEC standard package compatible with other standard 128Kb x 16 SRAMs.

SRAM N02L6181AB27I Features? Single supply range wide 1.65 to 2.2 volts? Very low standby current 0.5µA 1.8V (typical)? Very low operating current 1.4mA at 1.8V and 1µs (typical)? Page mode operation Very low current 0.5 at 1.8v and 1µs (typical)? Simple memory control MCU for independent enable (CE) byte control byte operation enable output (OE) memory expansion? Low voltage data retention Vcc = 1.2v? Access time 30 ns OE access time? Auto power down standby mode? Compatible with TTL tri-state output drivers? Space saving compact BGA package

Operating characteristics (over specified temperature range

1. Typical values are measured at Vcc=Vcc Typ. , TA=25℃, not 100% tested.

Max Cell Supply Voltage VCC 1.65 1.8 2.2 V Voltage VDR Chip Disabled2 Data Retention 1.2 - 2.2 V Input High Voltage VIH VCC VCC 0.7 + 0.3 V Input Low Voltage Vil -0.3 - 0.3 V Supply Voltage Output High Voltage VOH IOH = 0.2 ma VCC - 0.2 V Low Voltage Output Artificial Volume = -0.2 ma 0.3 V Input Leakage Current Ili VIN = 0 to 0.5 VCCµA Leakage Current Output ILO OE = VIH or Chip Disable 0.5µA Read/Write Operation Supply Current @ 1 Time2µs Period

2. The output is disabled when this parameter is specified to avoid external loading effects. The user must add the current required to drive the expected output capacitance in the actual system.

ICC1 SRAM N02L6181AB27I

VCC=2.2 V, VIN=VIH or VIL chip enabled, IOUT = 0 1.4 3.0 mA

Supply current for read and write operations @ 70 ns cycle time 2 ICC2

VCC=2.2 V, VIN=VIH or VIL chip enable, IOUT = 0 8.0 17.0 mA

Page Mode Operation Supply Current @ 70ns Cycle Time 2 (See Power Saving for Page Mode Operation Diagram)

ICC3

VCC=2.2V, VIN=VIH or enable VIL chip, IOUT = 0 2.0 4.0 mA

Read/Write Quiescent Operation Supply Current

3. If the chip is disabled (CE high), this device will assume standby mode. For low standby current, all inputs must be within 0.2 volts of VCC or VSS

ICC4VCC=2.2V, VIN=VIH or VIL chip enabled, IOUT = 0, f = 00.1 ma Maximum standby current t3 is b1VCC = VCC or 0V chip disabled tA=