MT48LC2M32B2 - 512K x 32 x 4 Bank DRAM MT48LC2M32B2P-6:G

DRAM MT48LC2M32B2P-6:G Features? PC100 Compatible? Fully Synchronized; All Signals Registered on Positive Edge of System Clock? Internal Pipelining; Column Address Can Change Every Clock Cycle? Burst length: 1, 2, 4, 8 or full page? Auto precharge including concurrent auto precharge and auto refresh mode? Self refresh mode (not on device)? Auto refresh - 64 ms, 4096-cycle refresh (commercial and industrial) - 16 ms, 4096 cycle refresh (automotive)? LVTTL-compatible inputs and outputs? Single 3.3 ± 0.3 V supply? 1, 2 and 3 DRAM with CAS latency (CL) support

Select Mark Meg? Configuration - 2 x 32 (512 kx 32 x 4 banks) 2 m32b2? Plastic Pack OCPL1 - 86 Pin TSOP II (400 ml) Standard TG - 86 Pin TSOP II (400 ml) Pb-free P - 90 Ball VFBGA (8mm x 13mm) Pbfree B5? Timing - Period 5 ns (200 MHz) 5 - 5.5 ns (183 MHz) -552 - 6 ns (167 MHz) 6 a3 - 6 ns (167 MHz) -62 - 7 ns (143 MHz) -72° Operating Temperature Range - Commercial (0°C + 70°C) No - Industrial (-40°C + 85°C) - Automotive (-40°C + 105°C) AT4? Revised: G /: J pointed out: 1. Unbalanced parting lines. 2. Applies to revision G.3 only. For J. 4 revision input clock only: CLK is driven by the system clock. All SDRAM input signals are sampled on the positive edge of CLK. CLK also increments the internal burst counter and controls the output registers. CKE Input Clock Enable: CKE activates (high) and deactivates (low) the CLK signal. Shutting down the clock provides precharge power-down and auto-refresh operation (all banks idle), active power-down (row activity in any bank), or clock suspend operation (burst/access in progress). CKE is synchronous, except after the device enters shutdown and self-refresh mode, and until exiting the same mode, CKE is asynchronous. Input buffers, including CLK, are disabled in power-down and self-refresh modes, providing low backup power. CKE may be tied high. c# input chip select: c# enable (register low) and disable (register high) command decoder. When cs# is high, all commands are masked, but read/write operations that are already in progress will continue, and when cs# is high, DQM operations will retain their DQ masking capabilities. cs# provides external banking options on several banking systems. CS# is considered part of the command code. DRAM MT48LC2M32B2P-6:G Input Commands: RAS#, CAS# and US# (along with CS#) define the input commands. DQM[3:0] Input Input Output Mask: DQM sampled high, is the input mask signal for write access and the output enable signal for read access. Input data is masked during write cycles. During the read cycle, the output buffer is in the high z state (two clock delays). DQM0 corresponds to DQ[7:0]; DQM1 corresponds to DQ[15:8]; DQM2 corresponds to DQ[23:16]; DQM3 corresponds to DQ[31:24]. DRAM DRAM MT48LC2M32B2P-6:G DQM[3:0] is considered the same state when referring to DQM. Enter Bank Address Input: Define which bank the Active, Read, Write or Precharge command applies to.