The memory AT27C020-70PC is a low-power, high-performance, 2,097, 152-bit, one-time programmable read-only memory (OTP EPROM) organized as 256K x 8 bits. In normal read mode, only a 5V power supply is required. Any byte can be accessed in less than 55ns, eliminating the need for reduced latency on high-performance microprocessor systems. In read mode, the memory AT27C020-70PC typically consumes 8mA. Standby mode supply current is typically less than 10µA. The AT27C020 is available in industry standard, JEDEC approved, One Time Programmable (OTP) PDIP and PLCC software packages. All devices feature two-wire control (CE, OE) to give designers the flexibility to prevent bus contention. The memory AT27C020-70PC has a storage capacity of 256K bytes, allowing the firmware to be stored reliably and the firmware can be accessed by the system without being delayed by mass storage media The memory AT27C020-70PC has additional features to ensure high quality and high Efficient production use. Fast programming algorithms reduce the time required for part programming and ensure programming reliability. The programming time is typically only 100µs/byte. Integrated product identification codes electronically identify devices and manufacturers. This feature is used by industry standard programming equipment to select the appropriate programming algorithm and voltage. Transient voltage excursions may occur when switching between active and standby states via the chip enable pin. Unless the system design allows, these transients may exceed data sheet limits and cause the device to fail. At least 0.1µf, high frequency, low inherent inductance, ceramic capacitors should be used for each device. This capacitor should be connected between the VCC and ground terminals of the device, as close as possible to the device. Also, to stabilize the supply voltage levels on the PCB with large EPROM arrays, most of the 4.7µf should be utilized with electrolytic capacitors, again connected between the VCC and ground terminals. The capacitors should be placed as close as possible to where the power supply is connected to the array where a 100 μs PGM pulse width is used to program. The address is set to the first location. VCC rises to 6.5V and VPP rises to 13.0V. Each address is the first program with a 100µs PGM pulse without verification. A verify/reprogram cycle is then performed for each address. If a byte fails verification, 10 consecutive 100µs pulses are applied after verification after each pulse. If the byte fails to verify after 10 pulses have been applied, the section is considered to have failed. After the bytes are properly verified, the next address will be selected until all addresses have been selected. Then reduce VPP to 5.0V and VCC to 5.0V. All bytes are read again and compared to the original data to determine if the device passed or failed.