? Features of DC Motor Clock Buffer CY2CC910OXI

At 3.3 V (see Figure 3) the parameters describe the condition Min Typ Max Unit VOH output high voltage VDD = min. , Clock Buffer CY2CC910OXI VIN = VIH or Verma IOH = -12 2.3 - 3.3 V Low Voltage Output Volume VDD = min. , Clock Buffer CY2CC910OXI VIN = VIH or Verma IOL = 12 0.2 0.5 V VIH Input High Voltage Guaranteed Logic High Level 2 5.8 V Ver Input Low Guaranteed Logic Low Voltage 0.8 V IHT Input High Current Low VDD = Max . VIN = 2.7 v 1µA IIL Input Low Current VDD = Max. VIN = 0.5 v 1μA Two Input High Current Low VDD = Max. VIN = VDD (Max) 20µA Vick Clamping Diode Voltage VDD = min. Including Ma = -18 -0.7 - -1.2 V IOK Continuous Clamping Current VDD = Max. Output Voltage = Ground - 50mA OOFF Power Save Disable VDD = Ground, Output Voltage = < 4.5v 100µA VH Input Hysteresis 80 mV

Clock Buffer CY2CC910OXI Features ■■Full support for low voltage operation: ?3.3 v? 2.5 v?1.8 v ■Overvoltage tolerant input thermally switchable ■1:10 split ■Drives 50 ohm or 75 ohm loads ■Low input capacitance ■Low output low propagation delay (less than 4 ns GM) ■■Typical high speed operation: ~200 MHz at 1.8V ~ 650 MHz industrial version for 2.5V and 3.3V ■■SSOP package available Description

The Cypress family of network circuits uses advanced 0.35-micron CMOS technology to implement the industry's fastest logic and buffers. The Cypress CY2CC910 fanout buffer has one input and 10 outputs. The conversion from 3.3V to 3.5V, 2.5V to 1.8V is ideal, which is designed for datacom clock management applications, and the large fanout of a single input reduces the loading of the input clock. Cypress uses a unique AVCMOS type output VOI (variable output impedance) to dynamically adjust variable impedance matching, eliminating the need for series damping resistors and reducing overall noise. At 2.5 V (see Figure 3) the parameters describe the condition Min Typ Max Unit VOH output high voltage VDD = min. , VIN = VIH or Vil IOH = 7 mA 1.8 V IOH = 12 mA 1.6 V Low Voltage Output Vol VDD = min. , VIN = VIH or Vil IOL = 12 Ma 0.65 V VIH Input High Voltage Guaranteed Logic Height 1.6 - 5.0 V Vail Input Low Level 0.8 V Low Voltage Guaranteed Logic Tt Input High Current Low VDD = Max. VIN = 2.4 v 1µA IIL Input Low Current VDD = Max. VIN = 0.5 v 1μA Two Input High Current Low VDD = Max. VIN = VDD (Max) 20µA Vick Clamping Diode Voltage VDD = min. Including Ma = -18 -0.7 - -1.2 V IOK Continuous Clamping Current VDD = Max. Output Voltage = Ground - 50mA OOFF Power Down Disable VDD = Ground, Output Voltage = < 4.5v 100µA VH Input Hysteresis 80 mV?