Features

● 125MSPS update rate

● Single power supply:+3.3V or+5V

● High SFDR: 70dB, FOUT 20MHz

] ● Low failure: 2pvs

● Low power: 310MW

● Internal reference

● Power off mode: 23MW

] ● Communication:

-Base, wireless LAN, Wireless LAN

-Base I/Q modulation

● Medical/test instruments

● Any waveform Generator (ARB)

● Direct digital synthesis (DDS)

Instructions

DAC2902 is a single, 12 -bit, dual channel, high -speed high -speed, high -speed high -speed speed The digital modular converter (DAC) can provide high dynamic performance after optimization, and the power consumption is only 310MW.

DAC2902 has a high update rate of up to 125msps, providing excellent dynamic performance, and can generate very high output frequency, which is suitable for direct intermediate frequency application. DAC2902 has optimized communication applications. In communication applications, processing separation rate I and Q data, while maintaining a close gain and offset matching.

Each DAC has a high impedance differential current output, which is suitable for single -end or differential analog output configuration.

DAC2902 combines high dynamic performance and high throughput, creating an economic efficient solution for various waveform synthetic applications:

Sex provides resolution of 10 -bit (DAC2900), 12 -bit (DAC2902) and 14 -bit (DAC2904).

pins are compatible with AD9765 dual DAC.

gain matching is usually 0.5%of the fulfillment, and the offset matching is specified to maximize 0.02%.

DAC2902 adopts advanced CMOS processes; segmented structure reduces the output fault energy to the minimum, and maximizes dynamic performance.

All digital inputs are+3.3V and+5V logic compatibility. DAC2902 has internal reference circuits and allows external reference.

DAC2902 is provided in tqfp-48 packaging, and is specified within the extended industrial temperature range -40 ° C to+85 ° C.

Preface Figure

Digital input and timing

DAC2902's data input port accepting standard coding, data bit D11 is the highest effective bit (MSB). The converter output supports the clock rate up to 125msps. The best performance is usually achieved through symmetrical writing and clock duty cycle; however, as long as the timing specification is met, the duty cycle may be different. In addition, settings and maintenance time can be selected within its stipulated restrictions.

All digital inputs in DAC2902 are compatible with CMOS. The logic threshold depends on the digital power voltage of the application, so they are set to about half of the power supply voltage; VTH +VD/2 (± 20%tolerance). DAC2902 is designed to work under the digital power supply (+VD) of+3.0V to+5.5V.

The two converter channels in the DAC2902 consist of two independent 12 -bit parallel data ports. Each Dacchaannel is input controlled by its own group (WRT1, WRT2) and clocks (CLK1, CLK2). Here, the WRT line control channel input lock memory, CLK line control DAC memory. The data is first loaded from the rising edge of the WRT line to the input lock. The next decline of the data is provided to the DAC memory in the WRT signal. At the next rising edge of the CLK line, DAC is updated with new data, and the simulation output signal will change accordingly. The dual -locking structure of the DAC2902 generates a definition sequence for WRT and CLK signals, which is represented by the parameter TCW . When the CLK rising edge appears at the same time or before or before the WRT signal rising edge, the correct timing is observed. Connecting the WRT and CLK lines can meet this condition. Note that all specifications are measured in the case of the WRT and CLK lines.

Typical features

TA 25 ° C,+vd +3.3V,+va +5V, differential transformer coupling, iOut 20mA, 50Y dual -end load, sfdr as high as nyquist Nyquist ,Unless otherwise indicated.

Application information

Operation theory

DAC2902's architecture structure Use current control technology to achieve fast switching and high update rates. The core component in a single DAC is a segmented current source array, which is designed to provide a full -scale output current of up to 20mA, as shown in Figure 1. The internal decoder addresss the differential current switch when the DAC is updated at a time of DAC, and forms a corresponding output current by turning all current to output and node iOut or iOUT. The complementary output provides the differential output signal. Reduce dynamic performance by reducing occasional harmonic, common mode signals (noise) and double peak output signals.

The segmented structure is significantly reducedFailure energy, improved dynamic performance (SFDR) and DNL. The current output keeps a very high output impedance greater than 200KY.

Full marking output current determines the ratio of internal reference voltage (about+1.25V) and an external resistor RSET. The IREF obtained is multiplied by the internal multiplied coefficient 32 to generate an effective DAC output current. The range of this current can be from 2mA to 20mA, depending on the value of the RSET.

DAC2902 is divided into digital parts and simulation parts, and each part is powered by its own power pins. The number parts include the input locks and decoder logic of the edge, and the simulation part includes the current source array and its related switches and reference circuits.

DAC transmission function

Each DAC in DAC2902 has a complementary current output iOUT1 and IOUT2.满标度输出电流IOUTFS是两个互补输出电流的总和：

单个输出电流取决于DAC代码，可以表示为：

[123 ]

Among them, #39; code #39; is a decimal representation of DAC data input words. In addition, IOUTFS is a reference current Iref function, which is determined by the reference voltage and external settings resistance RSET.

In most cases, the complementary output will drive the drive resistance load or terminal transformer. The signal voltage will be generated on each output according to the following conditions:

The load resistance value is limited by the DAC2902 output compliance specification. In order to maintain the specified linear performance, the voltage of iOut and IOUT should not exceed the maximum allowable compliance range.

The two single -end output voltage can be combined to obtain the total differential output swing:

Simulation output

DAC2902 provides provided Two complementary current output, iOUT and IOUT. The simplified circuit of the simulation output level of differential topology is shown in Figure 2. The output impedance of iOUT and iOUT is combined by parallel switch, current source and related parasitic capacitors.

The signal voltage may generate on the two outputs of iOut and iOUT. The negative value-1V is given by the breakdown voltage of the CMOS process. Exceeding this limit will affect the reliability of the DAC2902 and even cause permanent damage. When the full marking output is set to 20mA, the positive rules are equal to 1.25V, and the simulation power supply of+VA 5V is used. Please note that for the selection output current of iOUTFS 2mA,The scope of compliance is reduced to about 1V. It should be noted that the configuration of the DAC2902 does not exceed the scope of compliance to avoid decline in distortion and overall lineivity.

When the maximum full-scale output signal is limited to about 0.5VP-P, the best distortion performance can usually be obtained. 50 #8486; Double -end load and 20mA full -scale output current is the case. By selecting the appropriate transformer and maintaining the optimal voltage level of iOUT and iOUT at the same time, various loads can adapt to the output of DAC2902. In addition, the combination of differential output configurations with transformers will help achieve excellent distortion performance. Common model errors, such as even -order Harmon IC or noise, can be greatly reduced. This is especially true in the case of high output frequency.

For applications that require the best distortion and noise performance, it is recommended to choose the full standard output of 20mA. For applications that require low power consumption but tolerate slightly reduced performance levels, you can consider reducing the range of full range to 2mA.

Output configuration

The current output of DAC2902 allows multiple configurations, some of which are shown in Table 1. As mentioned earlier, the use of the differential output of the converter will generate the best dynamic performance. This differential output circuit can be composed of RF transformer or differential amplifier configuration. The transformer configuration is the ideal configuration of most AC coupling applications, and the operational amplifier will be suitable for DC coupling configuration.

For applications that require a single output voltage, you can consider single -end configuration. Connect a resistor from any output to ground, and convert the output current into a ground reference voltage signal. In order to improve DC linearity by maintaining virtual grounding, I-TO-V or op amp configuration can be considered.

Transformer differential movement

The use of RF transformer provides a convenient way to convert the difference output signal into a single -end signal, and at the same time achieve excellent dynamic performance (see Figure 3). Select the appropriate transformer carefully according to the output spectrum and impedance requirements. The advantage of the configuration of differential transformers is to significantly reduce the co -mode signal, thereby improving the dynamic performance within the wide frequency range. In addition, by selecting the appropriate impedance ratio (winding ratio), the transformer can provide the best impedance matching, and at the same time control the soft voltage of the converter output. The model ADTT1-1 (via miniature circuit) has a ratio of 1: 1 and can be used to connect to DAC2902 and 50 #8486; load. This will lead to the load of each output iOUT and IOUT to 25 #8486; The output signal is a communication coupling and inherently inherent due to its magnetic coupling.

As shown in Figure 3, the center tap of the transformer is grounded. This forced the voltage to swing on iOut and iOUT centered on 0V. In this case, the two resistors RL can be replaced with an RDiff or completely omitted. Only when all components approach each otherAnd when the Bobby is not important, this method should be used. The complete power transmission from DAC output to load can be achieved, but the range of output is compliant. Alternatively, if the center tap is not connected, the signal swing will be located in the center of RL IOUTFS/2. However, in this case, two resistors (RL) must be used to enable the necessary DC current for two outputs.

Differential configuration of the operation amplifier

If the application requires DC coupling output, you can consider using the differential amplifier, as shown in Figure 4. The configuration differential amplifier requires four differential feedback amplifiers as an operational amplifier. Under the configuration, DAC2902 generates a 0.5VP-P differential output signal at the load resistor RL. The selected resistance value is to make each current output generate 25 #8486; symmetrical load, because the input impedance of the differential amplifier is connected with the resistance RL, so it should be considered.

OPA680 configuration to gain to 2. Therefore, the use of 20mA full -scale output operation DAC2902 will generate a voltage output of ± 1V. This requires the amplifier to work in the case of dual power (± 5V). The tolerance of the resistor usually sets the limit that can achieve co -mode suppression. It can be improved by fine -tuning resistor R4.

This configuration usually provides lower AC performance than the transformer solution discussed earlier, because the amplifier introduces another distortion source. Select the appropriate amplifier ability according to its conversion rate, harmonic distortion and output swing. High-can consider using a speed amplifier like OPA680 or OPA687. The AC performance of this circuit can be improved by adding a small capacitor (CDiff) between the output and the output end, as shown in Figure 4. This will introduce a solid point to create a low -pass filter to limit the rapid output signal level of DAC, otherwise it may drive the amplifier to enter the conversion limit or overload state; both will cause excessive distortion. This differential amplifier can be easily modified to increase the application of a single -end output voltage as a single -end output voltage, that is, swing between 0V and+2V.

Dual -cross -resistant output configuration

The circuit example in FIG. 5 shows the signal output current connected to the dual voltage feedback amplifier OPA2680. Or I-TO-V Converter . With this circuit, the output of DAC will be kept on a virtual ground to minimize the impact of the output impedance change, thereby obtaining the best DC linearity (INL). As mentioned earlier, be careful not to drive the amplifier to the conversion rate limit and produce unnecessary distortion.

The DC gain of the circuit is equal to the feedback resistor RF. In high frequency, DAC output impedance (CD1. CD2) 0 will generate 0 in the noise gain of OPA2680, which may cause the peak of the closed -loop frequency response. Increase radio frequency gain to compensate for peak noise. In order to achieve a flat cross -resistance frequency response, the pole points in each feedback network should be set to:

Use GBP OPA's gain bandwidth,

Its rotation frequency F-3DB is about:

Full marking output voltage is defined only by iOutfs RF, and has negative orders. In order to improve the AC performance of the circuit, the adjustment of radio frequency and/or output power needs to be considered. Further expansion of this application instance can include adding a differential filter at the output of OPA2680, and then add a transformer to convert it to a single -end signal.

Single -end configuration

Use a load resistance connected to a DAC output, a simple current voltage conversion can be completed. The circuit in FIG. 6 shows the 50 #8486; the resistor connected to iOT, providing a terminal for further connected 50 #8486; cables. Therefore, when the nominal output current is 20mA, the DAC will generate a total signal of 0V to 0.5V in the load of 25 #8486.

As long as it does not exceed the output range, you can choose different load resistance values. In addition, the output current iOUTFS and the load resistance can be adjusted to provide each other to provide the required output signal amplitude and performance.

The interface simulation positive traffic device

One of the main applications of dual -channel DAC is transmission of baseband i and Q channel for digital communication. In this application, the DAC is followed by analog orthogonal maker, which uses the base with data to modify the IF carrier, as shown in Figure 7. Generally, the input stage of these positive transiters consists of a NPN crystal tube. These transistors need a DC bias (base) voltage greater than 0.8V. The wide output conformity range (–10V to+1.25V) allows direct DC coupling between DAC2902 and orthogonal makers.

FIG. 8 shows an example of a DC coupling interface and DC level offset using a precision resistance network. As shown in Figure 9, the advantage of the coupling interface is that the co -mode level of the modulator input terminal can be set by the co -mode level of the DAC output end.

In addition, there is no voltage loss in the device.

Internal reference operation

DAC2902 has a film reference circuit, which includes 1.25V gap benchmark and two control amplifiers, each DAC. DAC2902's full standard output current IOUTFS is determined by reference voltage, VREF, and resistance RSET. IOUTF can pass throughCalculation of the following formula:

The external resistance RSET is connected to the FSA pin (full marking adjustment), as shown in Figure 10. The reference control amplifier works as a V-I converter to generate reference current. Iref is determined by the ratio of VREF and RSET (as shown in equal 10). The full marked output current IOUTFS is obtained by Iref by a fixed factor 32.

When using internal reference, 2K #8486; resistance value will generate a full standard output of about 20mA. Considering a resistor with a tolerance of 1%or higher. Choose a higher value, the output current can be adjusted from 20mA to 2mA. Out of reducing total power consumption, optimizing distortion performance, or observing output compliance voltage restrictions under the given load conditions, it may be desirable to operate DAC2902 under the output current below 20mA.

It is recommended to use 0.1 μF or higher ceramic chip capacitor to bypass the Refin pin. Control the internal compensation of the amplifier, and its small signal bandwidth is about 0.3MHz. gain setting options

Full standard output current on DAC2902 can be set in two ways: set each channel setting in two DAC channels alone, or set up two channels at the same time, set up two channels settings settings Essence For the independent gain setting mode, the GSET pin (pin 42) must be low (that is, connected to Agnd). In this mode, two external resistors-one RSET is connected to the FSA1 pin (pin 44), and the other is connected to the FSA2 pin (pin 41). In this configuration, users can flexibly set and adjust the full standard output current of each DAC, allowing compensation for the possible gains that may be matched in other places in the transmitting signal path.

Or, the GSET pin is high (that is, connect to+VA), and the DAC2902 will be switched to the synchronous gain setting mode. At present, the full standard output current of the two DAC channels is determined by only an external RSET resistor connected to the FSA1 pin. The resistor at the FSA2 pin can be removed, but this is not necessary, because the pin does not work in this mode, and the resistor does not affect the gain equation. The formula of the correct RSET remains unchanged. For example, RSET 2KY will generate 20mA output for two DACs.

External reference operation

You only need to apply an external reference voltage on the REFIN tube foot, you can disable internal reference. In this example 11 shown. For applications that require higher accuracy and drift performance, or increase the ability to control dynamic gain control, you can consider using external benchmarks.

Although it is recommended to use 0.1 μF capacitors for internal benchmarks, the capacitor is optional for external benchmark operation. Reference input reFIN has high input impedance (1M #8486;), which can be easily driven by various power supply. Note that the voltage range of the external benchmark should be kept within the reference input compliance range (0.5V to 1.25V).

Power off mode

DAC2902 has a power -off function, which can be used to reduce the total power current below 6mA. Application logic on PD pin will start power -off mode, while low logic is enabled by normal operation. When keeping the interruption, the inside -oriented pull -down circuit will enable the converter to work normally.

grounding, decoupling and layout information

Correct grounding and bypass, short -drawing length and ground layer use are particularly important for high -frequency design. Multi -layer printing circuit boards are recommended to the best performance because they have significant advantages, such as minimizing ground impedance, separation of signal layers from ground layers, etc.

DAC2902 uses separate pins for its analog and digital power supply and grounding connection. The position of the decoupling capacitor should ensure the simulation power supply (+VA) bypass to the analog ground (AGND), and the digital power bypass to the digital grounding (DGND). In most cases, 0.1 μF ceramics capacitors at the foot of each power are enough to provide low impedance decoupling paths. Keep in mind that their effectiveness depends to a large extent on the degree of approximation of a single power and ground pins. Therefore, these wires should be as close as possible. As long as it is possible, the capacitor should be directly below each pair of power/ground pins on the back of the PC board. This layout method will minimize the parasitic inductance of the minimum component and the PCB line.

Further power supply to add a further power supply to the surface of the converter and the surface of the surface with the surface of the converter (1 μF to 4.7μF) can be added to the converter.

All power and grounding connections of DAC2902 require low noise. It is recommended to use a multi -layer PCB with independent power and ground layers. Mixed signal design requires special attention to the wiring of different power currents and signal trajectories. Generally speaking, the simulation power and ground layers should only extend to the analog signal area, such as DAC output signals and reference signals. Digital power and ground layers must be limited to the area covering digital circuits, including digital input cables connected to the converter and clock signals. The analog and digital ground layer should be connected by a point below the DAC. This can be implemented by about 1/8 inches (3 mm).

Power supply to DAC2902 by using wide PCB lines or planes. The width current will provide lower tracking impedance to further optimize the power decoupling. The simulation and digital power supply of the converter can only be connected by the power connector of the PC board. In the case of only one power supply voltage to supply DAC, you can use iron oxygen magnet beads and bypass electric containers to create LC filters. This will generate a low noise simulation power supply voltage, and then can be connected to the+VA power pins of the DAC2902.

In the design layout, it is important to keep the simulation signal trajectory separated from any digital line to prevent noise coupling on the analog signal path.

Packaging drawings