PCI Interface IC/PI7C9X440SLBFDE PCI Express-to-usb 2.0 host controller complies with PCI Express Base Specification Revision 1.1, Open Host Controller Interface Specification Revision 1.0, Enhanced Host Controller Interface Specification Revision 1.0. The high-performance architecture of the PCI interface IC/PI7C9X440SLBFDE can connect from one PCIe x1 upstream port to four USB 2.0 ports. This device extends the connectivity domain of the system by allowing simultaneous access to multiple USB devices from the system host processor. The device's USB port can support all available speeds, including High Speed (HS), Full Speed (FS) and Low Speed (LS). The device's PCIeto-USB2.0 bridge function is implemented by two host controllers, the Enhanced Host Controller Interface (EHCI) and the Open Host Controller Interface (OHCI). There is one EHCI controller and two OHCI controllers in the PCI interface IC/PI7C9X440SLBFDE. The EHCI controller handles high-speed USB transactions, while the OHCI controller handles full-speed or low-speed USB transactions.

PCI Interface IC/PI7C9X440SLBFDE PCI Express-to-usb 2.0 host controller complies with PCI Express Base Specification Revision 1.1, Open Host Controller Interface Specification Revision 1.0, Enhanced Host Controller Interface Specification Revision 1.0. The high-performance architecture of the PCI interface IC/PI7C9X440SLBFDE can connect from one PCIe x1 upstream port to four USB 2.0 ports. This device extends the connectivity domain of the system by allowing simultaneous access to multiple USB devices from the system host processor. The device's USB port can support all available speeds, including High Speed (HS), Full Speed (FS) and Low Speed (LS). The device's PCIeto-USB2.0 bridge function is implemented by two host controllers, the Enhanced Host Controller Interface (EHCI) and the Open Host Controller Interface (OHCI). There is one EHCI controller and two OHCI controllers in PI7C9X440SL. The EHCI controller handles high-speed USB transactions, while the OHCI controller handles full-speed or low-speed USB transactions.

From the system model, the device contains two cascaded virtual PCI-to-PCI bridges, with the upstream port bridge on the downstream port bridge on the virtual PCI bus, and the three USB controllers connected to the downstream PCI Express ports. During the enumeration process, the internal PCIe upstream and downstream ports are assigned unique bus numbers, device numbers, and function numbers, which logically form a target ID. Through the boot process, the USB host controller is treated as a multifunction device. Assign function #2 to the EHCI controller, function #0 and function #1 to both OHCI controllers, and assign the same device number to all controllers. Memory maps and IO address ranges are assigned exclusively to each port and USB host controller. After software enumeration is complete, the transaction packet is routed to a dedicated PCIe port or USB host controller based on the embedded content of the address or target ID.