Gate Driver CSD97396Q4M Synchronous Buck NexFET? Power Stage

1. Over 93% System Efficiency on 15 A Ultrabook/Notebook DC/DC Converter; and Computing System? High Density - Son 3.5mm x 4.5mm Footprint? Ultra Low Inductance Package The driver CSD97396Q4M NexFET™ power stage is an ultra-low quiescent (ULQ) current mode highly optimized design compatible with high power, high 3.3 V and 5 V density synchronous buck converter PWM signals. This product integrates the driver chip and NexFET technology, and realizes the power stage switching function in the diode emulation mode and FCCM. The driver chip with input voltage up to 24v has built-in optional diode emulation tri-state PWM input function, which enables DCM operation to improve light load efficiency. In addition, the driver IC supports ?Integrated boot diode ULQ mode, supports connected standby? Shoot-through protection Windows?8. Tri-state of PWM input", "lead-free certified - lead-free plated termination quiescent current reduced to 130μA, immediate response. When skipping #hold tri-state", "halogen-free current is reduced to 8µA (typically takes 20µs to restore switching). This combination produces a high current, high efficiency, high speed switching device in a small 3.5 x 4.5 mm profile package. Additionally, the PCB footprint has been optimized to help reduce design time and simplify the design of the complete system. The power stage driver CSD97396Q4M is a highly optimized design for synchronous buck applications using NexFET devices with 5 V gate drivers. Control Field Effect Transistor (FET) and Synchronous Field Effect Transistor (FET) silicon are parametrically tuned to produce the lowest power loss and highest system efficiency.

The driver CSD97396Q4M external VDD voltage needs to provide the integrated gate driver IC and provide the necessary gate driver power supply for the mosfet. A 1µF 10 V X5R or higher ceramic capacitor is recommended to bypass the VDD PGND pin. It also includes a bootstrap circuit that provides gate drive power for the control field effect transistor. The boot supply to drive the control FET is generated by connecting a 100nf 16v X5R ceramic capacitor between the BOOT and BOOT_R pins. An optional RBOOT resistor can be used to slow down the turn-on speed of the control FET and reduce voltage spikes on the VSW node. A typical value of 1Ω to 4.7Ω is a compromise between switching losses and VSW peak amplitude.

7.3.2 Under Voltage Lockout (UVLO) Protection The UVLO comparator evaluates the VDD voltage level. As VVDD increases, the control FET and sync FET gates remain low until VVDD reaches the higher UVLO threshold (VUVLO_H). , then the driver starts working and responds to PWM and skip # commands. If VDD falls below the lower UVLO threshold (VUVLO_L = VUVLO_H - hysteresis), the device will disable the driver and actively drive the control FET and sync FET gate outputs low