The video IC/TVP5150AM1PBSR decoder converts baseband analog video to digital YCbCr 4:2:2 component video. Combo and S-video inputs are supported. The TVP5150AM1 decoder includes a 9-bit analog-to-digital converter (ADC) with a sampling multiple of 2×. Sampling is ITU-R BT.601 (27.0 MHz, generated by a crystal or oscillator input at 14.31818 MHz) and is wire-locked. With embedded synchronization, the output format can be 8-bit 4:2:2 or 8-bit ITU-R BT.656.

The video IC/TVP5150AM1PBSR decoder utilizes Texas Instruments' patented technology to lock onto weak, noisy or unstable signals. Generates a Genlock/real-time control (RTC) output for synchronizing downstream video encoders.

Complementary four-line adaptive comb filtering for both luma and chroma data paths reduces cross-luminance and cross-chroma artifacts; chroma trap filters are also available.

Video characteristics including hue, brightness, saturation and sharpness can be programmed using the industry standard I2C serial interface. In addition to digital video output, the video IC/TVP5150AM1PBSR decoder can also generate sync, blanking, lock and clock signals. The TVP5150AM1 decoder includes an advanced vertical blanking interval (VBI) data retrieval method. The VBI data processor slices, parses, and error checks data in teletext, closed headers, and several other formats. The TVP5150AM1 decoder detects copy-protected input signals according to the Macrovision® standard and detects types 1, 2, 3 and colorstripe processes.

The main modules of the video IC/TVP5150AM1PBSR decoder include:? Robust synchronous detector? ADC analog processor? Y/C separation using up to adaptive comb filter? Chroma processor? Luma processor? Video clock/time processing Converter and power saving control output formatter? VBI data processor? Macrovision I2C interface to detect composite and super video

The TVP5150AM1 decoder has one analog input channel that accepts two ac-coupled video inputs. The decoder supports a maximum input voltage range of 0.75 V; therefore, for most input signals with a peak-to-peak variation of 1.5 V, half attenuation is required. 75Ω is recommended for input devices before nominal parallel termination. See the application diagram in Figure 6-1 for recommended configurations. Two analog input ports can be connected as: ? two optional combo video inputs ? one s-video input

An internal clamp circuit restores the sync end of the ac-coupled video signal to a fixed DC level.

A programmable gain amplifier (PGA) and an automatic gain control (AGC) algorithm work together to ensure that the input signal is sufficiently amplified to ensure the correct input range of the ADC.

The ADC has 9 bits of resolution and runs at a nominal speed of 27mhz. The clock input to the ADC comes from the horizontal phase-locked loop