The battery voltage monitoring mode is enabled by setting bit VBAT_MONI_CHx = 1 in the FLEX_VBAT_CN register. Additionally, the instrumentation amplifier for the selected channel must be turned off by setting SHDN_INA_CHx = 1 in the AFE_SHDN_CN register. In this mode, the positive input POSx of the sigma-delta modulator will sample the voltage provided on the VDD pin. At the same time, the negative input NEGx of the sigma-delta modulator will sample the reference voltage VREF generated on or supplied to the CVREF pin. Therefore, the output signal of the sigma-delta modulator is a measure of (VBAT-VREF). In this operation, the gain factor is corrected while the sigmadelta modulator is operating, and the battery voltage VBAT can be calculated as follows:

⑴ 100% _ weighing factor (defined by the supplier according to its workload distribution)

In the formula, if the internal reference voltage generator is used, VREF = 2.4 V, and ADCMAX is the maximum output code of the ADC, which corresponds to the theoretical 2.4 V signal at the input of the sigma-delta modulator. The value of ADCMAX depends on the configuration of the digital filter, and the corresponding ADCMAX values are listed in Table 8 to Table 11. The battery monitor mode operates the system on batteries in the voltage range of 2.4 V to 4.8 V. When the ADS1293 is powered by a regulated 5-V supply, the battery monitor mode cannot be used because it risks saturating the sigma-delta modulator. There is also a low battery alarm, implemented independently of the battery monitoring mode, that triggers a battery alarm when the supply voltage falls below 2.7 V (see BATLOW description for the alarm function).

8.3.3 Test Mode

If the battery voltage monitoring feature is not enabled, and if bit TSTx = 01 (see the Input Channel Select Register section), a positive DC test signal is provided to the input of the instrumentation amplifier. If TSTx = 10, the same test signal is provided, but with negative polarity. The expected ADC output code can be calculated as follows:

(2)

In Equation 2, the positive or negative DC test signal VTEST = VREF/12. Note that this test mode is not a gain calibration, as VTEST and VREF are generated from the same reference; however, it can be used as a self-test or to measure gain mismatch between channels.

When TSTx = 11, the input of the instrumentation amplifier in the channel can be shorted to provide a zero test signal. The desired ADC output code equation can be simplified to:

(3)

For both equations, the ADCMAX values for a given decimation configuration can be found in Tables 8 through 11.

8.3.4 Analog Front End

The ADS1293 contains three analog front ends that convert differential analog voltages to digital signals. Each analog front end consists of an instrumentation amplifier (INA), a sigma-delta modulator (SDM), and a digital filter.

8.3.5 Instrumentation Amplifier (INA)

Instrumentation amplifiers provide a high input impedance interface for signal sources that may have relatively high output impedance, such as ECG electrodes. The maximum differential input voltage range of the Sigma-Delta Modulator (SDM) after the INA is ±1.4 V, and the INA has a gain of 3.5x. Therefore, the maximum differential input voltage of the INA is ±400mv