The LT?1280A/LT1281A are dual RS232 driver/receiver pairs with an integrated charge pump to generate RS232 voltage levels from a 5V supply. These circuits feature a rugged bipolar design that provides operational fault tolerance and ESD protection unmatched by competing CMOS designs. Using only 0.1µf external capacitors, these circuits consume only 40mW of power and can even drive up to 120kbaud with heavy capacitive loads. The new on-chip ESD structure enables the LT1280A/LT1281A to withstand multiple ±10kV strikes, eliminating the need for expensive TransZorbs™ on the RS232 pins. The LT1280A/LT1281A are fully compliant with the EIA RS232 standard. The drive output is overload protected and can be shorted to ground or ±30V without damage. In the event of a shutdown or power loss, the outputs of the driver and receiver are in a high impedance state, allowing line sharing. The LT1281A is available in 16-pin DIP and SO packages. The LT1280A is available as an 18-pin DIP so it is suitable for applications that require shutdown 10 mamax supply current at ±10 kv Small capacitor for ESD protection: 0.1 μf 120 k baud operation RL = 3 k CL = 2500 pf ■ 250 k baud operation RL = 3 k CL = 1000 pf Withstand ±30 V without breakage ■ ■ Output CMOS Comparable Low Power: 40 mw ■ ■ Operates from a 5 V supply Biphasic Emotional Design ■ ■ Rugged output assumes a high impedance Status when closed or closed ■ Meets all available RS232 specifications ■ ■ With or without shutdown Absolutely no closed ■ This packs usable logic input current 0.8 V ≤ VIN ≤ 2.0 V 5 20 μ output short circuit current output voltage V = 0 ± 9 17 mA output Leakage Current Shutdown Output Voltage = ±30 V (Note 4) 100 μA Data Rate (Note 7) RL = 3 k CL = 2500 pf 120 k Baud, RL = 3 k CL = 1000 pf 250 k Baud Slew Rate RL = 3 k CL = 51 pf 15 30 V/µs RL = 3 k, CL = 2500 pf 4 7 V/µs Propagation Delay Output Transition tHL Intraday (Note 5) 0.6 - 1.3 µs Output Transition by Low 0.5 - 1.3 Hysterectomy μs Receiver Input Voltage Threshold Input Low Threshold (Output Voltage = High) Class C 0.8 - 1.3 V Input High Threshold (Output Voltage = Low) Class C 1.7 - 2.4 V Input Low I Grade 0.2 - 1.3 V Input High I Grade Hysteresis 0.1 0.4 1.0 1.7 - 3.0 V Input Resistance VIN = ±10 V 3 5 7 kΩ Leakage Current Output Off (Note 4) 0 ≤ Output Voltage ≤ VCC 1 10µ Output Voltage Output Low, IOUT = -1.6 mA 0.2 - 0.4 V Output High, IOUT = 160µa (VCC = 5 V) 3.5 - 4.2 V Output Short Circuit Current Consumption Current, Output Voltage = VCC -20 -10 mA Sourcing Current, Voltage Output = 0 V 10 20 mA Spread Delay Output Transition tHL Intraday (Note 6) 250 600 ns Output Transition Hysterectomy 350 600 ns by Low Note 4: Power supply current measured with Von/Off ≤ 0.1 V. Note 5: For driver latency measurements, RL = 3k, CL = 51pF. The trigger point is set between the driver's input logic threshold and the output transition to zero (tHL = 1.4V to 0V, tLH = 1.4V to 0V). Note 6: For receiver delay measurements, CL = 51pF. The trigger point is set between the receiver input logic threshold and the output transition to standard TTL/CMOS logic threshold (tHL = 1.3V ~ 2.4V, tLH = 1.7V ~ 0.8V). Note 7: Rotation rate, short circuit current, and propagation delay tests guarantee data rate operation