is clocked into the FPGA during each cycle. These configuration schemes significantly reduce configuration time compared to traditional schemes. Additionally, EPC devices have dynamic configuration or page mode features. This feature allows you to dynamically reconfigure all FPGAs in the system with a new image stored in configuration memory. Up to 8 different system configurations or pages can be stored in memory using PGM[2..]0]. Your system can be dynamically reconfigured by selecting one of the eight pages and initiating a reconfiguration cycle. This page mode feature, combined with an external flash interface, allows remote and local updating of system configuration data. EPC equipment conforms to the remote system configuration characteristics of hierarchical equipment. Other user-programmable features include:? Real-time compression of configuration data? Programmable Flash ISP configuration clock (DCLK)?? Programmable motion delay (PORSEL) related information? EPC devices, configuration devices provide more information on PCN0506: Intel's Flash as a Stratix Device Handbook. FPGA configuration FPGA configuration is managed by the configuration controller chip. The process includes reading the configuration data from flash, decompressing the configuration data, transferring the configuration data using the appropriate data[] pins, and handling error conditions. After POR, the controller determines user-defined configuration options by reading its option bits from flash. These options include configuration scheme, configuration clock speed, decompression, and configuration page settings. The option bits are stored at flash address location 0x8000 (word address), occupying 512 bits or 32 words of memory. These option bits are read using the internal flash interface and the default 10mhz internal oscillator. After the configuration controller chip has acquired the configuration settings, it checks whether the FPGA is ready to accept configuration data by monitoring the nSTATUS and con_done signals. When the FPGA is ready (nSTATUS high con_done low), the controller starts data transfer using DCLK and data[] output pins. The controller selects the configuration page[2.]0] POR or post-reset pins to transfer to the FPGA by sampling the FPGA's PGM. The function of the configuration unit is to transfer the decompressed data to the FPGA according to the configuration scheme. The EPC device supports four concurrent configuration modes, n = 1, 2, 4, or 8 (where n is the number of bits sent per DCLK cycle for the data[n] signal). The value n=1 corresponds to the conventional PS configuration scheme. n = 2, 4 and 8 correspond to concurrent configurations of 2, 4 or 8 different PS configuration chains, respectively. Additionally, the FPGA can be configured in FPP mode where 8 bits of data are locked in the FPGA per DCLK cycle