The write status operation code is b0000 0001, which lists the MSB first. Use the write status operation to set the status register block protection bits. Write status operations do not affect other bits. Therefore, this can be implemented to protect certain memory sectors, as shown in Table 9 to Table 13. After the block protection bit is set, protected memory sectors are considered read-only memory. You must perform a write enable operation before the write status operation so that the device sets the write enable latch bit of the status register to 1. A write status operation is accomplished by driving the nCS signal low, then shifting the write status operation code and one data byte from the status register on the ASDI pin. Figure 10 shows the instruction sequence for the write status operation. After the 8th bit of the data byte is locked, nc must be driven high, otherwise the write status operation will not be performed. Immediately after the nCS signal is driven at high speed, the device starts a self-timed write state cycle. The self-timed write status cycle for all EPCS devices typically takes 5 ms and is guaranteed to be less than 15 ms. For more information, see the tWS values in Table 16 on page 29. You must account for this delay to ensure that the status register is written with the required block protection bits. Alternatively, you can perform a read status operation while the self-timed write status loop is in progress to check the writing bit in the status register. During a self-timed write status cycle, the in-progress write bit is 1, and the completion is 0? The erase sector operation code is b1101 1000, which lists the MSB first. This operation allows you to erase a sector in an EPCS device by setting all bits within the sector to 1 or 0xFF. This is useful if you want to access unused sectors as general memory in your application. The write enable operation must be performed before the erase sector operation in order to set the write enable latch bit in the status register to 1. You can implement an erase sector operation, first drive the nCS signal low, then move in the erase sector operation code, then select the three address bytes of the sector on the ASDI pin. The three address bytes used for the erase sector operation can be any address within the specified sector. For more information on sector address ranges, see Table 3 on page 7 through Table 7 on page 12. After the eighth bit of the erase sector operation code has been locked, the nCS signal is driven high. Immediately after the nCS signal is driven high, the device initiates an automatic timed erasing sector cycle. See the tES value in Table 16 on page 29 for details on the auto-timed erase sector cycle time. This delay must be accounted for before accessing the memory contents. Alternatively, you can perform a read status operation while the self-timed erase sector cycle is in progress to check the write progress bit in the status register. The write progress bit is set to 1 during an auto-timed erase sector cycle and set to 0 when complete. The write enable latch bit in the status register is reset to 0 before the erase cycle is complete.

?In the AS configuration, the FPGA acts as the configuration main program in the configuration flow to provide the clock for the EPCS device. The FPGA uses the nCSO signal shown in Figure 2 and Figure 3 to pull down the nCS signal to implement the EPCS device. The FPGA then sends the command and address to the EPCS device using the ASDO signal. The EPCS device responds to the command by sending configuration data to the FPGA DATA0 pin on the falling edge of DCLK. Data is latched to the falling edge of the FPGA's next DCLK signal.

1 Before the FPGA enters configuration mode, make sure that the EPCS device VCC is ready. If VCC is not ready, you must keep nCONFIG low until all power rails for the EPCS device are ready.

The FPGA controls the nSTATUS and con_done pins during configuration in AS mode. If the con_done signal does not go high at the end of configuration, or if the signal goes high too early, the FPGA pulses its nSTATUS pin low to initiate reconfiguration. If the configuration is successful, the FPGA releases the con_done pin, allowing the external 10-k resistor to pull the con_done signal high. FPGA initialization starts after the con_done pin goes high. After initialization, the FPGA enters user mode.

For more information on configuring FPGAs into configuration mode or other configuration modes, see the configuration chapter in the appropriate device manual