Cyclone™ devices contain a two-dimensional row- and column-based architecture to implement custom logic. Column and row interconnects at different speeds provide signal interconnection between lab and embedded memory blocks.

The logic array consists of labs with 10 LEs in each lab. LE is a small logic unit that provides efficient implementation of user logic functions. Labs are divided into rows and columns across devices. Cyclone devices range from 2910 to 2060 LEs.

M4K RAM blocks are true dual-ported memory blocks with 4K memory plus parity (4,608 bits). These blocks provide dedicated true dual port, simple dual port, or single port memory up to 36 bits wide and up to 250 MHz. The blocks are grouped across devices between some labs

The Quartus II compiler creates carry chains of more than 10 LEs by automatically linking labs together. For enhanced fitting, long carry chains run vertically, allowing fast horizontal connections to M4K memory blocks. The carry chain can extend all the way to the entire column.

Clear and Preset Logic Controls the logic for clearing and presetting signals in a lab-wide signal control register. LE directly supports asynchronous clear and preset functions. Register presetting is accomplished by asynchronously loading a logic high. Direct asynchronous presets do not require NOT pushback techniques. Cyclone devices support simultaneous preset/asynchronous loads and clear signals. If both signals are asserted at the same time, the asynchronous clear signal takes precedence. Each lab supports up to two clears and one preset signal.

In addition to the clear and preset ports, the Cyclone device provides a chip-wide reset pin (DEV_CLRn) that resets all registers in the device. In the Quartus II software, a precompile option set controls this pin. This chip-wide reset overrides all other control signals.

Multi-channel interconnection