In the AS configuration, the FPGA acts as the configuration main program in the configuration flow, providing the clock for the EPCS device. The FPGA uses the nCSO signal shown in Figure 2 and Figure 3 to pull down the nCS signal to implement the EPCS device. The FPGA then sends the command and address to the EPCS device using the ASDO signal. The EPCS device responds to the command by sending configuration data to the FPGA DATA0 pin on the falling edge of DCLK. Data is latched to the falling edge of the FPGA's next DCLK signal.

1 Before the FPGA enters configuration mode, make sure that the EPCS device VCC is ready. If VCC is not ready, you must keep nCONFIG low until all power rails for the EPCS device are ready.

The FPGA controls the nSTATUS and con_done pins during configuration in AS mode. If the con_done signal does not go high at the end of configuration, or if the signal goes high too early, the FPGA pulses its nSTATUS pin low to initiate reconfiguration. If the configuration is successful, the FPGA releases the con_done pin, allowing the external 10-k resistor to pull the con_done signal high. FPGA initialization starts after the con_done pin goes high. After initialization, the FPGA enters user mode.

For more information on configuring FPGAs into configuration mode or other configuration modes, see the configuration chapter in the appropriate device manual. The write byte operation code is b0000 0010, which lists MSB first. This operation allows writing bytes to memory. A write enable operation must be performed before a write byte operation to set the write enable latch bit in the status register to 1. A write byte operation is accomplished by driving the nCS signal low, followed by the write byte operation code, three address bytes, and at least one data byte on the ASDI pin. If the 8 LSBs (A[7..0]) are not all 0, then all transmit data beyond the end of the current page will not be written to the next page. Instead, the data is written at the starting address of the same page (from an address where all 8 LSBs are 0). If more than 256 data bytes are transferred into the EPCS device using a write byte operation, the previously locked data is discarded and the last 256 bytes are written to the page. However, if fewer than 256 bytes of data are translated to the EPCS device, those bytes are guaranteed to be written at the specified address and do not affect other bytes of the same page. If your design needs to write more than 256 data bytes to memory, multiple memory pages are required. Before writing a new page, send the write enable and write bytes operation codes, followed by three new target address bytes and 256 data bytes. The nCS signal must be driven high after the 8th bit of the last data byte is latched. Otherwise, the device will not perform the write byte operation. The write enable latch bit in the status register is reset to 0 before each write byte operation is completed. Therefore, the write enable operation must be performed before the next write byte operation. Immediately after the nCS signal is driven high, the device initiates a timed write cycle. See the tWB value in Table 16 on page 29 for more information on auto-timed write cycle times. This amount of delay must be taken into account before writing to another page of memory. Alternatively, you can perform a read status operation while a self-timed write cycle is in progress, thereby checking the writing-in-progress bit in the status register. During a self-timed write cycle, the writing bit is set to 1 and is set to 0 when completed.