High Performance RISC CPU:?C Compiler Optimized Architecture??Only 49 Instructions Operation Speed:- DC 20 MHz Clock Input- DC-200 ns Instruction Cycle Underflow reset? Direct, indirect and relative addressing modes: - Two full 16-bit File Select Registers (FSRs) - Market readable program and data memory Flexible oscillator structure: ~ 16 MHz internal oscillator Blocks: - Typical factory calibrated ±1% - Software selectable frequency range from 16 MHz to 31 kHz? 31 kHz low power internal oscillator? Three external clock modes 20 MHz special microcontroller Features: :- 1.8 v to 3.6 v (PIC12LF1501) - 2.3 v to 5.5 v (PIC12F1501)? Under software control Self-Programmable? Power-on reset()? Boost timer (PWRT)? Reset (LPBOR)? Extended Watchdog Timer (WDT): - Programmable period from 1 to 256S ms?? In-Line Programmable Code Protection Serial Programming? (ICSP?) via two pins? Enhanced Low Voltage Programming Software (LVP)? Debugger (ICD) via two pins? Power Save Sleep Mode: Low Power Sleep Mode - Low Power BOR (LPBOR)? Integrated Temperature Indicator? Endurance (minimum) memory: 1 Kwords linear program memory addressing 64 bytes linear data memory addressing High Endurance Flash Data Memory (HEF) - 128 bytes if non-volatile data storage - 100k erase/write cycle

Ultra Low Power (XLP) Features (PIC12LF1501): Sleep Current:- 20na @ 1.8V, typical Watchdog Timer Current:- 260 nA @ 1.8V, typical Operating Current:- 30a/MHz @ 1.8V ,typical

Peripheral features: Analog-to-digital converter (ADC): - 10-bit resolution Four external channels - Three internal channels: - Fixed voltage reference digital-to-analog converter (DAC) - Temperature indicator channel Auto acquisition function converts in Available during sleep? Digital-to-Analog Converter (DAC): - Output available with external positive reference select Internal Comparator connection and ADC? Fixed reference voltage (FVR) with 1x, 2x and 4x output levels obtained? 6 I/O pins (1 handler pin): 25 - High current sink/source mA / 25 mA - Individually programmable weak leads Body-up individually programmable Interrupt-on-Change (IOC) pins? Timer0: 8-bit and 8-bit programmable timer/counter prescaler? Enhanced Timer1:- 16-bit timer/counter and prescaler - External gate input Modes? Timer 2: 8-bit timer/counter with 8-bit period register, prescaler and postscaler? Four 10-bit PWM modules

The program counter (PC) is 15 bits wide. The low byte comes from the PCL register, which is a readable and writable register. The high byte (PC<14:8>) is not directly readable or writable, it comes from PCLATH. On any reset, the PC is cleared. Figure 3-3 shows five cases of PC loading.

Figure 3-3: PC loading in different situations

3.4.1 Modify the PCL that executes any instruction that targets the PCL register, while replacing the program counter PC<14:8> bits (PCH) with the contents of the PCLATH register. This allows the entire contents of the program counter to be changed by writing the desired upper 7 bits to the PCLATH register. When the lower 8 bits are written to the PCL register, all 15 bits of the program counter are changed to the value contained in the PCLATH register and the value being written to the PCL register.

Add an offset to the program counter (ADDWF PCL) after calculation to complete the calculation backward. When using the computed GOTO method to perform table reads, care should be taken if table locations cross PCL memory boundaries (each 256-byte block). See Application Note AN556, "Implementing Table Reads" (DS00556). Computing function calls allows programs to maintain function tables and provides another way to execute a state machine or lookup table. When executing tables read using compute function calls, care should be taken if table locations cross PCL memory boundaries (each 256-byte block). If a call instruction is used, the PCH<2:0> and PCL registers are loaded with the operands of the call instruction. PCH<6:3> is loaded with PCLATH<6:3>. The CALLW instruction supports compute calls by combining PCLATH and W to form the target address. The call to the calculation is done by loading the W register with the desired address and executing the call. The PCL register is loaded with the W value, and the PCH is loaded with PCLATH. 3.4.4 Branches Branch instructions add an offset to the PC. This allows for relocatable code and code that spans page boundaries. There are two branch forms, BRW and BRA. In both cases, the PC will increase the number of times it fetches the next instruction. PCL memory boundaries may be crossed when any branch instruction is used. If using BRW, load the W register with the desired unsigned address and execute BRW. The entire PC will be loaded with address PC+1+w, if BRA is used, the entire PC will be loaded with PC+1+, which is the BRA instruction operation