When TC < 0°C, IDD2P and IDD3P must be reduced by 6%; IDD4R and IDD4W must be reduced by +4%; IDD7 must be reduced by +11%. When TC > 85℃: IDD0, IDD1, IDD2N, IDD2NT, IDD2Q, IDD3N, IDD3P, IDD4R, IDD4W, IDD5R must be reduced by 3%; IDD2P must be reduced by 40%. 5. When additional delay is enabled for IDD1, the current change is about +4%. 6. When additional delay is enabled for IDD2N, the current change is about 0%. 7. When the IDD2N disables the DLL, the current changes by about -23%. 8. When CAL enables IDD2N, the current change is about -25%. 9. When downshifting is enabled for IDD2N, the current change is about 0%. 10. When CA parity is enabled for IDD2N, the current change is about +7%. 11. IPP3N tests and limits apply to all IDD2x, IDD3x, IDD4x, IDD6x, IDD8 conditions; that is, testing IPP3N should meet the requirements of IPPs for known IDD tests. 12. When additional delay is enabled for IDD3N, the current change is about +0.6%. 13. When additional delay is enabled for IDD4R, the current change is about +5%.

TwinDie?1.2V DDR4 SDRAM MT40A1G16 - 64 Meg x 16 x 16 bank x 1

Description 16Gb (TwinDie?) DDR4 SDRAM uses Micron's 8Gb DDR4 SDRAM die; two x8s combined into one x16. Similar signals to mono x16, with an additional ZQ connection for faster ZQ calibration and a BG1 control for x8 addressing. For specifications not included in this document, please refer to Micron's 8Gb DDR4 SDRAM datasheet (x8 option). Specifications for base part number MT40A1G8 are related to two separate manufacturing part numbers MT40A1G16. Features? Use two x 8 8 gb microns to die one x16? Single-level TwinDie? VDD = VDDQ = 1.2 v 1.2 (1.14 - -1.26 v)? VDDQ-terminated I/O? TC 0°C to 95°C - 0°C to 85°C: 8192 refresh cycles 64 ms - 85°C to 95°C: 8192 refresh cycles 32

Option Marks Configuration - 64 Meg x 16 x 16 bank x 1 rank 1G16 96 ball FBGA package (no pb) - 9.5mm x 14mm x 1.2mm Die RPM: A HBA - 8.0mm x 14mm x 1.2mm Die RPM: B , D WBU - 7.5mm x 13.5mm 1.2mm Dead Priest: E KNR? Timing - Period time1 0.625 ns @ CL = 22 (ddr4-3200) -062 E - 0.682 ns @ CL = 21 (ddr4-2933) -068 - 0.750 ns @ CL = 19 (ddr4 - 2666) -075 - 0.750 ns @ CL = 18 (ddr4 - 2666) -075 E - 0.833 ns @ CL = 17 (ddr4 - 2400) -083 - 0.833 ns @ CL = 16 ( ddr4-2400) -083 E - 0.937 ns @ CL = 15 (ddr4 - 2133) -093 E - 1.071 ns @ CL = 13 (ddr4 - 1866) -107 E? Self Refresh - Standard? Operating Temperature No Commercial (0° C TC≤≤95°C)