?CDCLVC11xx 3.3-V and 2.5-V LVCMOS High-Performance Clock Buffers Family 1 Feature 1? High-Performance 1:2, 1:3, 1:4, 1:6, 1:8, 1:10, 1:12 LVCMOS Clock buffer family? Very low this slope < 50 p? Additive very low jitter < 100 fs? Supply voltage: 3.3 V and 2.5 V? fmax = 250 MHz to 3.3 V fmax = 180 MHz 2.5 V? °C to 85°C? in 8-14-16-20-24-pin TSSOP package (all Pin-Compatible)

General purpose communications, industrial and consumer applications

The CDCLVC11xx is a family of modular, high-performance, low-skew, general-purpose clock buffers from Texas Instruments.

The entire home is designed with modularity in mind. It is to complete TI's family of LVCMOS clock generators.

Seven different fanout variations, 1:2 to 1:12, are available. All devices are pin compatible for easy operation.

All family members share the same high performance features such as low additive jitter, low skew and wide operating temperature range.

The CDCLVC11xx supports an asynchronous output enable control (1G) that switches the output to a low state when 1G is low.

The CDCLVC11xx family operates in 2.5 v and 3.3 v environments and is characterized for operation between -40°C and 85°C.

The low additive jitter of the CDCLVC11xx can be shown in the previous application example. A low noise 100 MHz XO with 26-fs RMS jitter drives the CDCLVC11xx, resulting in 86-fs RMS jitter integrated from 12 kHz to 20 MHz. The resulting additional jitter is a low 82-fs RMS for this configuration.

10 Power Supply Recommendations

High-performance clock buffers are sensitive to noise on the power supply, which can significantly increase the buffer's additive jitter. Therefore, it is necessary to reduce the noise of the system power supply, especially when jitter and phase noise are critical to the application.

Filter capacitors are used to eliminate low frequency noise in the power supply, and bypass capacitors provide a very low impedance path for high frequency noise, protecting the power system from induced fluctuations. These bypass capacitors also provide the equipment needed for transient current surges and should have low equivalent series resistance (ESR). For proper use of bypass capacitors, they must be placed close to the power terminals and have short loops to reduce inductance. TI recommends adding as many high frequency (eg, 0.1µF) bypass capacitors as possible, with supply terminations in the package. TI recommends, but does not require, inserting ferrite beads between the board power supply and the chip power supply to isolate high frequency switching noise from the clock buffer; these beads prevent switching noise from leaking into the board power supply. A proper ferrite bead with very low DC resistance must be chosen to provide adequate isolation between board power and chip power, as well as to maintain the voltage at the supply terminals above the minimum voltage required for proper operation.

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