1 feature 1? Isolated bidirectional, I2C compatible, communicator? Supports up to 1 MHz operation? 3v 5.5 - v? C operating temperature? ±50-kV/μs transient immunity (typical)? HBM ESD protected 4 kV pin; VRMS Isolation / UL 1577 1 Minute - CSA Certified / IEC 60950-1 and IEC 62368-1 Terminal Equipment Standards - CQC Basic Insulation / GB4943.1-2011

2 Applications? Isolated I2C bus? SMBus and PMBus interface? Open drain network? Motor control system? Battery management? I2C level shifting

The ISO1540 and ISO1541 are low-power bidirectional isolators that are compatible with the I2C interface. The logic input and output buffers of these devices are separated by TI capacitive isolation technology using a silicon dioxide (SiO2) barrier. When used with isolated power supplies, these devices block high voltages, isolate grounds, and prevent noise currents from entering local grounds, interfering with or damaging sensitive circuits.

Compared to optocouplers, this isolation technology offers advantages in functionality, performance, size, and power consumption. ISO1540 and ISO1541 devices enable a complete isolated I2C interface to be implemented within a small form factor.

The ISO1540 has two independent bidirectional channels for clock and data lines, while the ISO1541 has one bidirectional data and unidirectional clock channel. ISO1541 is suitable for applications with only one main program, while ISO1540 is suitable for multi-machine applications. For applications that are scalable from the clock, ISO1540 devices should be used.

Isolated bidirectional communication is accomplished in these devices, preventing the internal logic present in standard digital isolators by offsetting the low-level output voltage on Side 1 to a value greater than the high-level input voltage on Side 1 Latches.

The master process starts the transaction by creating a START condition, followed by the 7-bit address of the slave process it wishes to communicate with. Then there is a read and write (R/W) bit that indicates whether the master wants to write 0 or read from slave 1. The master process then releases the SDA line to allow the slave process to acknowledge the received data.

The slave responds by acknowledging that some (ACK) takes the SDA pin low for the entire high time of 9 in the sci clock pulse, after which the master is still in transmit or receive mode (transmit according to R/W), while the slave continues in complement mode (receive or transmission).

The address and 8-bit data bytes are sent most significant bit (MSB) first. The start bit is represented by a high-to-low transition of SDA, while SCL is high. The stop condition is a low-to-high transition of SDA while SCL is high.

If the master writes to a slave, it repeatedly sends a byte with the slave sending an ACK bit. In this example, the master server is in master transmit mode and the slave server is in slave receive mode.

If the master process reads data from the slave process, it repeatedly receives a byte from the slave process while acknowledging (ACK) the receipt of every byte except the last (see Figure 29). In this case, the master server is in master receive mode and the slave server is in slave transmit mode.

The master ends the transfer with a stop bit, or can send another start bit to maintain bus control for further transfers.

Figure 29. Transmit or receive mode changed during data transfer

When writing to the slave, the master mainly works in transmit mode, and only switches to receive mode when the slave receives a response.

When reading data from a slave, the master starts in transmit mode, then switches to receive mode after sending a read request to the slave (R/W bit = 1). The slave continues to operate in supplemental mode until the end of the transaction.