DDR2 SDRAM uses a double data rate architecture to achieve high speed operation. The double data rate architecture is essentially a 4n prefetch architecture with an interface designed to transfer two data words per clock cycle on the I/O ball. A read or write operation of DDR2 SDRAM actually consists of a 4n-bit wide, two-clock-cycle data transfer on the internal DRAM core and four corresponding n-bit-wide, one-half clock cycles on the I/O balls composition of data transmission. A bidirectional data strobe (DQS, DQS#) is transmitted externally with the data to capture the data at the receiving end. DQS is a strobe transmitted by DDR2 SDRAM during reads and the memory controller during writes. DQS is edge-aligned with data for reads and center-aligned with data for writes. The x16 provides two data strobes, one for the lower byte (LDQS, LDQS#) and the other for the upper byte (UDQS, UDQS#). DDR2 SDRAM operates through differential clocks (CK and CK#); the intersection of CK going high and CK# going low is called the positive side of CK. Commands (address and control signals) are registered on each positive edge of CK. Input data is registered on two sides of DQS, and output data is referenced to two sides of DQS and two sides of CK. Read and write accesses to DDR2 SDRAM are burst-oriented; accesses start at a selected location and continue in program order for the program number of locations. Access first registers an ACTIVATE command, and then registers a READ or WRITE command. The address bits registered with the ACTIVATE command are used to select the bank and line to be accessed. The address bits registered in line with the read or write command are used to select the starting column location for bank and burst access. DDR2 SDRAM offers programmable read or write burst lengths of 4 or 8 locations. DDR2 SDRAM supports interrupting a burst read of 8 with another read or interrupting a burst write of 8 with another write. The auto-precharge feature can be enabled to provide automatic timed row pre-charge that starts at the end of a burst access. Like standard DDR SDRAM, the pipelined multi-bank architecture of DDR2 SDRAM supports concurrent operation, providing high effective bandwidth by hiding row precharge and activation times. Provides self-refresh mode and power-saving and power-down modes. All inputs are compatible with the JEDEC standard of SSTL_18. All drive strength outputs are sstl_18 compatible.