Features

Quick throughput: 1 MSPS

VDD for 2.7 V to 5.25 V

Low power consumption under maximum throughput:

When VDD 3 V, the maximum 4 mW

maximum 9.25 mW, 1 msps, VDD 5 v

Input bandwidth: Input frequency is 100 kHz, 70 db sinad

Flexible power/serial clock speed management

No pipeline delay

High -speed serial interface: SPI # 174;-/qspi #8482;-/Weis #8482;-/DSP compatibility

Power off mode: maximum 1 μA

8-lead-23 and MSOP packaging

Application

Sensor interface

battery power supply system

Data collection system

Portable instrument General description [ 123]

AD7441

/

AD7451

is 10-/12-bit high-speed, low power consumption, single power supply, approaching one by one (SAR) and modulus converter (ADC), with pseudo Simulate input. The working voltage of these components is 2.7 volt to 5.25 volts, and it achieves extremely low power consumption at a high throughput of up to 1 millisecond/second.

AD7441/AD7451 contains a low noise, broad band width, differential tracking (T/H) amplifier, which can process the input frequency of up to 3.5 MHz. The reference voltage of these devices is applied to the VREF pin from the outside, and its range from 100 MV to VDD depends on the power supply and suitable application.

The conversion process and data collection are controlled by CS and serial clocks, allowing the device to be a microprocessor or DSP interface. At the beginning of the conversion, the input signal is sampled along the CS decrease. The SAR architecture of these parts ensures that there is no delay in pipeline.

Product Highlights

1. Use 2.7 V to 5.25 V power supply.

2. High throughput, low power consumption. AD7441/AD7451 uses a 3V power supply, which provides a maximum power consumption of 4MW with a throughput of 1 MSPS.

3. Pseudo -separation simulation input.

4. Flexible power/serial clock speed management. The conversion rate is determined by serial clock. When the conversion time is reduced by increased the speed of the serial clock, the allowable power is reduced. These components also have a shutdown mode, with a maximum limit under lower throughputImprove power efficiency.

5. Reference input of variable voltage.

6. No pipeline delay.

7. Input and control the sampling moment with CS input and one -time conversion control.

8, ENOB GT; 10 bits, the typical reference voltage is 500 MV.

Function box diagram

Typical performance features

[[] [

123] TA 25 ° C, FS 1 MSPS, FSCLK 18 MHz, VDD 2.7 V to 5.25 V, VREF 2.5 V, unless otherwise explained.

The term

signal -to -noise ratio

This is the Sinad measured on the ADC output end ratio. The signal is the average root amplitude of Kobo. Noise is the sum of all non -basic signals. It does not exceed half of the sampling frequency (f/2), excluding DC electricity. This ratio depends on the quantitative level during the digitalization process: the more levels, the smaller the quantitative noise.对于具有正弦波输入的理想N位转换器，理论SINAD比由：

因此，对于12位转换器，SINAD为74db；对于10位转换器， Sinad is 62DB.

Total harmonic distortion (THD)

THD is the ratio of harmonic equity and the ratio of the base wave. In AD7441/AD7451, THD is

: V1 is the average root amplitude of the Kobe. V2, V3, V4, V5, and V6 are the average root amplitude of the second to sixth harmonic.

Peak harmonic or strange noise

The maximum bandal value of the base frequency harmonic value (excluding ADC) is defined as the maximum of ADC. Under normal circumstances, the value of this specification is determined by the largest harmonic in the spectrum, but this is a peak of noise for the ADC buried in the noise layer.

Mutual distortion

When the input consists of two frequencies (FA and FB) sine waves, non -linear active devices are Products of distortion, where M, N 0, 1, 2, 3, are pushed according to this. Mutual disturbances refer to the items that M and N are not equal to zero. For example, the second order includes (FA+FB) and (FA FB), and the third -order item includes (2FA+FB), (2FA FB), (FA+2FB), (FA ; 2FB).

AD7441/AD7451 uses the CCIF standard for testing, two of which are close to the top of the input bandwidth. In this case, the frequency of the second -order item is usually far from the original sine wave, and the frequency of the third -order item is usually close to the input frequency. Therefore, the second and third -order items are specified separately. Mutual disturbance is performed according to the THD specification. Among them, it is the ratio of the RMS of a single distortion product to the sum of the general principle of basic principles. It is represented by a decibel.

Aperture latency

This is the time of the actual sampling time from the sampling clock to ADC.

Pore diameter jitter

This is the change of samples on the actual sample of the actual sampling.

Full power bandwidth

The full power bandwidth of ADC refers to the input frequency. At this frequency, the reconstructed base wave amplitude is reduced by 0.1DB or 3DB (for full scale input).

Integral non -linearity

This is the maximum deviation from the straight line that transmits the end point of the function through the ADC.

Differential non -linearity (DNL)

This is the difference between the measurement between any two adjacent code in ADC and the ideal 1 LSB change.

The offset error

This is the deviation of the first code conversion (000 ... 000 to 000 ... 001) and the ideal state (that is, Agnd+1 LSB).

gain error

This is the last code conversion (111 ... 110 to 111 ... 111) after the offset error adjustment (ie vREF 1 LSB).

Tracking and maintaining the collection time

Tracking and keeping the collection time is to keep the amplifier in the tracking mode, so that the output to reach and stabilize the required within the 0.5 LSB range of the application input signal. shortest time.

Power suppression ratio

Power suppression ratio is defined as a full-standard frequency (f) the power output at the ADC output at the ADC VDD power supply that is applied to the frequency FS Compare. The frequency of this input ranges from 1 kHz to 1 MHz.

Among them:

PF is the power at the ADC output mid -frequency F.

PFS is the power under the ADC output mid -frequency FS.

Operation theory

Circuit information

AD7441/AD7451 is 10-/12 bits, high-speed, low power consumption, single power supply, approaching one by one, pseudo-pseudo-differential simulation input input Model converter (ADC). These components use a 2.7 volt to 5.25 voltsPower supply, when using 18 MMS SCLK power supply, its throughput can reach 1 millisecond/second. AD7441/AD7451 needs to be used for external reference for VREF pin.

AD7441/AD7451 has a SAR ADC, a differential tracking of a film, and a serial interface, located in the 8-line SOT-23 or MSOP package. The serial clock inputs the data from the component and provides the clock source for SAR ADC. AD7441/AD7451 has a power -off option to reduce the power consumption between conversion. The power -off function is implemented through the standard serial interface, as described in the operation mode.

Inverter operation

AD7441/AD7451 is a SAR ADC based on two capacitive DACs. Figure 19 and 20 show the simplified schematic diagram of the ADC during the collection and conversion phase, respectively. ADC consists of controlling logic, one SAR and two capacitive DACs. In Figure 19 (the collection stage), SW3 is closed, SW1 and SW2 are in position A, the comparator is kept in a balanced state, and the differential signal of the input of the input of the capacitor arrays.

When the ADC starts to convert (see Figure 20), SW3 is opened, SW1 and SW2 move to position B, causing the comparator to become unbalanced. After the conversion starts, the two inputs are disconnected. Control logic and charge re -assigning DACs to add and subtract a fixed amount of charge from the sampling capacitance array to make the comparator return to the balance state. When the comparator is re -balance, the conversion is completed. Control logic to generate ADC output code. The output impedance of the source of the driver VIN+and VIN-pins must be matched; otherwise the stable time of the two inputs will cause errors.

ADC transmission function

AD7441/AD7451 output encoding is direct (natural) binary. The design code conversion occurs under the continuous LSB value (1LSB, 2LSB, etc.). The LSB size of AD7451 is VREF/4096, and the LSB size of AD7441 is VREF/1024. The ideal transmission characteristics of AD7441/AD7451 are shown in Figure 21.

Typical wiring chart

FIG. 22 shows the typical connection chart of the device. In this settings, the GND pins are connected to the simulation ground layer of the system. The VREF pin is connected to the AD780, and the AD780 is a 2.5V decoupling reference source. The signal source is connected to the VIN+analog input through the unit gain buffer. Connect the DC voltage to the VIN -pin and provide pseudo -connecting places for VIN+input. Use 10 μF 钽 capacitors and 0.1 μF ceramic capacitors to decide the VDD foot with Agnd. Use a capacitor with at least 0.1 μF to decide with Agnd.The conversion result is output with 16 -bit words, 4 of which is zero -lead, and the latter is MSB with 12 or 10 -bit results. The 10 bits of AD7441 follow the two tails.

Input of analog quantity

AD7441/AD7451 with a pseudo -differential simulation input. VIN+input and signal source coupling must have an amplitude of VP-P to use the entire dynamic range of the component. DC input is applied to VREF. The voltage applied to the input provides a ground-shift or pseudo-connected ground for VIN-input. The pseudo -split input separates the analog input signal with ADC, allowing the DC co -modulus voltage.

Since ADC is powered by a single power supply, it is necessary to set the ground bipolar signal level offset to meet the input requirements. The operational amplifier (for example, AD8021) can be configured to a redirect signal (double pole) signal to make it compatible with the input range of AD7441/AD7451 (see Figure 23).

When the conversion occurs, the pseudo -land corresponds to 0, and the maximum simulation input corresponds to 4096 and 1024 of AD7451 and 1024 of AD7441.

Simulation input structure

Figure 24 shows the equivalent circuit of AD7441/AD7451 analog input structure. The four diode provides ESD protection for analog input. It must be noted that the analog input signal will not exceed 300 millivoltkenly. This causes these diodes to be pressed forward and starts to the substrate. These diode can transmit up to 10 mAh instead of irreversible damage to the parts. C1 capacitor (see Figure 24) is usually 4 PF, which is mainly due to the pipe capacitor. The resistor is a concentrated component composed of the switching resistor of the switch. The value of these resistors is usually about 100Ω. The C2 capacitor is an ADC sampling capacitor, usually with 16 PF capacitors.

For communication applications, it is recommended to remove high -frequency components from the analog input signal on the related simulation input pins. In applications where harmonic distortion and signal -to -noise ratio are very important, it is recommended to simulate the simulation input from low resistance resistance. Large source impedance will significantly affect the ADC's AC performance, which requires using input buffer amplifiers. The choice of amplifier is a function of a specific application.

When no amplifier is used to drive analog input, it is recommended to limit the source impedance at a low value. The maximum source of impedance depends on the total harmonic distortion of the tolerance. THD increases with the increase of source impedance and decrease in performance.

FIG. 25 shows the relationship diagram of THD and analog input signal frequency under different sources of impedance.

FIGThe rate is 1 MSPS and SCLK is 18 MHz. In this case, the source impedance is 10Ω.

Digital input

Digital input applied to AD7441/AD7451 is not limited by the maximum rated value of simulation input. Instead, the number of digital inputs, that is, CS and SCLK can reach 7V, and are not limited by VDD+0.3V restrictions on the analog input. The main advantage of input is not subject to VDD+0.3V restrictions is to avoid the problem of power sorting. If CS or SCLK is applied before VDD, there will be no atresia risk, because when the signal is greater than 0.3V before the VDD, the simulation input will appear to be locked.

References

It is necessary to provide reference for external power supply for AD7441/AD7451. The range of the reference input is from 100 mlock to VDD. For the power supply of 2.7 V to 5.25 V, the prescribed reference voltage is 2.5 V. The reference input for the selection of the application must not be greater than the power supply. The error in the reference source will cause the gain error in the AD7441/AD7451 transmission function, and increase the specified full marking error of the component. A capacitor must be placed on VREFPIN at least 0.1 μF. The appropriate reference sources of AD7441/AD7451 include AD780 and ADR421. Figure 27 shows a typical connection diagram of the VREF pin.

Serial interface

Figure 2 and 3 show the detailed time -sequencing diagram of AD7451 and AD7441 serial interface. The serial clock provides a conversion clock and control data transmission from the device during the conversion.

CS starts the conversion process and sets the data transmission frame.

The decline of the CS keeps the orbit enters the maintenance mode and leaves the bus from three states. Sample the analog input, and start to change at this time. The conversion requires 16 SCLK cycles to complete.

Once the 13 SCLK drops appear, track and keep it back to the tracking mode in the next SCLK rising edge, as shown in point B in Figure 2 and 3. In the 16th SCLK, the SDATA cable returned to three states.

If the CS rising edge appears before 16 SCLK, the conversion is terminated and the SDATA line returns to 3 states.

The conversion results from AD7441/AD7451 are provided on the SDATA output as a serial data stream. These positions are output along the clock in the SCLK input. The data stream of AD7451 is composed of four pre -guided zero and 12 -bit conversion data, which provides MSB first. The data stream of AD7441 is composed of four front -to -zero -to -zero -to -zero data. The latter is 10 -bit conversion data, and the latter is two followers. This is first provided to MSB. Under these twoThe output codes are direct (natural) binary.

Performing the conversion requires 16 serial clock cycles and access data from AD7441/AD7451. CS turns the first front guide to read DSP or microcontroller. Then, the remaining data starts from the second front guide, and the subsequent SCLK decreases along the time. Therefore, the first descending clock edge on the serial clock provides a second front guide. The last one in the data transmission is valid in the 16th decline edge, and the drop along the first (15) decline is punch -in. Once the conversion is completed, and the data is accessed after the 16 clock cycle, it is important to ensure that before starting the next conversion, there is sufficient time to meet the collection and quiet time specifications (see Timing Example 1 and Time Example 2 parts). In order to use the 18MHz clock to achieve 1 MSPS, the 18 clock pulse string executes the conversion, and leave enough time to collect and quiet time before the next conversion.

In applications with slower SCLK, you can read the data on the CS decrease along the CS decrease of the edge of the CS, and the 15th SCLK edge edge of each SCLK is provided, and the 15th SCLK edge of the edge of SCLK Provides DB0.

Timing Example 1

FSCLK 18MHz, throughput is 1msps, the cycle time is:

The cycle includes:

123]

Therefore, if T2 10 NS,

These 296 nan seconds meet the tacit requirements of 290 nan seconds.

As can be seen from Figure 28, the tacit understanding includes:

T8 35ns. This allows the value of TQUIET to 122 ns to meet the minimum requirements of 60ns.

Timing Example 2

If FSCLK 5 MHz and 315 KSPS throughput, then the cycle time is:

The cycle includes:

Therefore, if T2 is 10 ns, then

This 664 NS meets the tacit understanding of 290 ns. From Figure 28, the tacit understanding includes:

T8 35ns. This allows the value of TQUIET to 129 ns to meet the minimum requirements of 60ns.

In this example, and other slower clock values, the signal can be obtained before the conversion is completed, but it still needs to leave the minimum value of 60 ns between the conversion. In the Example 2, the approximately C is obtained at the approximate C point C in FIG. 28Signal.

Operation mode

The working mode of AD7441/AD7451 is selected by controlling the logical state of the CS signal during the conversion period. There are two working modes: normal mode and power -off mode. After the conversion starts, the point of the CS is pulled determines whether the component enters the power -off mode.

Similarly, if the power is off, the CS control device will resume normal operation or keep power off. These modes provide flexible power management options, which can optimize power/throughput ratio for different application requirements.

Normal mode

This mode is used to achieve the fastest throughput performance. When AD7441/AD7451 is always fully powered, users do not have to worry about any power -on time. Figure 29 shows the schematic diagram of AD7441/AD7451 in this mode. The conversion starts at the decline of the CS (see the serial interface part). To ensure that the parts are fully powered, the CS must be kept at a lower position until the CS decreases and passes at least 10 SCLK decrease edges.

If CS is at a high level at any time before the 16th SCLK decreases at the 16th SCLK, the component is kept power -on, but the conversion terminal is terminated, and the SDATA returns to three states. Completing and accessing complete conversion requires 16 serial clock cycle results. CS can be high until the next conversion, or some time before the next conversion. Once the data transmission is completed, that is, when SDATA returns to three states, another conversion can be started after a quiet time TQUIET, so that the CS is lower.

Power off mode

This mode is applicable to applications that require lower throughput; turn off the ADC between each conversion, or use high throughput with high throughput A series of conversions are executed, and then the ADC is turned off for a relatively long period of time. When the AD7441/AD7451 is in the power -off mode, all analog circuits are disconnected. In order to make the AD7441/AD7451 enter the power -off mode, the conversion process must be interrupted. After the second decline of SCLK and the tenth decline edge before, the CS is high, as shown in Figure 30.

Once the CS is at a high level in the SCLKS window, the parts enter the power -off state, the conversion of the CS decrease is terminated, and the SDATA returns to three states. The time from CS to SDATA three -state enabled time is never greater than T8 (see chapters). If the timing specification CS becomes high before the second SCLK decreases, the parts will remain in the normal mode and will not be powered off. This avoids accidental power off due to the CS line failure.

To exit the power loss mode and connect the power supply of the AD7441/AD7451 again,Execute virtual conversion. At the decline of the CS, the device starts to power. As long as the CS remains at a low position, until the 10th SCLK declines edges, the device will continue to power. After the device is completely powered on after 1 μs, as shown in China, the next conversion generates valid data.

If the CS before the 10th decrease of SCLK is at a high level, the AD7441/AD7451 will enter the power -off state again. This avoids accidents caused by accidents caused by failure or low CS on the CS line or the lower accidents of the 8 SCLK cycle. Therefore, although the device may start power at the CS decrease, as long as it occurs before the 10th SCLK decline edge, it will once again power off at the CS rise. Powering time

AD7441/AD7451 is usually 1 μs, which means that when the frequency of SCLK is as high as 18MHz, a virtual cycle is always enough to allow equipment to power. Once the virtual cycle is completed, the ADC will be fully powered and the input signal is correctly obtained. Static time TQUIET must still allow the next fall edge of CS from the bus from the virtual conversion to the point of the three states.

When running with a maximum throughput of 1 MSPS, AD7441/AD7451 has a signal of ± 0.5 LSB in a virtual cycle (ie 1 μs). When the power -off mode with a virtual circulation is powered on, as shown in Figure 31, when the parts are powered off, it is tracked and maintained to return to the tracking mode SCLK edge parts after the first time. As shown in point A in Figure 31.

Although a virtual cycle is sufficient to power the device and obtain VIN at any SCLK frequency, it does not necessarily mean that it must always pass through the complete virtual cycle of 16 SCLKs and obtain VIN completely; 1 μs is enough to power on power. Equipment and get input signals.

For example, when the 5MHz SCLK frequency is applied to ADC, the cycle time is 3.2 μs (ie 1/(5MHz) × 16). In a virtual cycle, 3.2 μs, components are powered on, and VIN is fully obtained. However, after using 1 μs of 5MHz SCLK, only 5 SCLK cycles have been passed. At this stage, ADC has been fully powered and obtained signals. Therefore, in this case, CS can rise after the 10th SCLK decline, and then decrease again after a time TQUIET to start the conversion.

When the power supply is first applied to AD7441/AD7451, the ADC can be powered on in the power failure mode or normal mode. Therefore, it is best to allow a virtual cycle to ensure that parts are fully powered before trying effective conversion. Similarly, if the user wants the parts to power off in the power off mode, then the virtual cycle can be used to ensure that the device is in the power -off modeThe method is the loop shown in Figure 30. Once powers to AD7441/AD7451, the power -on time is the same as the time for power -off mode. Under normal mode, it requires about 1 μs. Before performing a virtual cycle, no need to wait 1 μs to ensure the required operation mode. Instead, after power supply to ADC, the fake cycle can occur directly. If the first effective conversion is executed after the virtual conversion, you must pay attention to ensure that sufficient collection time is allowed.

As mentioned earlier, when the power -off mode is powered on, the component returns to the tracking mode at the edge of the first SCLK to use it after the CS decrease. However, when the ADC starts to power on power after the power is turned on, the tracking remains in the tracking mode. This means (assuming that there is a device that monitor ADC power currents), if ADC is powered on by the required operation mode, there is no need to change the mode. Therefore, it is not necessary to place the track and keep it on the orbit.

Power and throughput

By using the power -off mode on the device when not converted, the average power consumption of ADC decreases lower at a lower throughput. Figure 32 shows how the device maintains a longer period of time when the throughput is reduced, and the average power consumption is reduced accordingly. For example, if AD7441/AD7451 works in continuous sampling mode with a throughput of 100KSPS and 18MHz SCLK, and the device is in the power off mode between the conversion, the power consumption during normal operation is 9.25mW (for VDD 5V) Essence

If the power -on time is a virtual cycle (1 μs), and the remaining conversion time is another cycle (1 μs), then it can be said that AD7441/AD7451 consumes 9.25 mW in each conversion cycle and lasts 2 μs. (This power consumption data assumes that the time to enter the power -off mode is very short. As the number of clock pulses used to enter the power -off mode increase, this power value will increase). The remaining 8 μs of AD7441/AD7451 is only 5 μW.

Calculate the number of power in Figure 32 as follows:

If the throughput 100KSPS, the cycle time 10 μs, the average power consumed per cycle is:

]

In the same case, if VDD 3V, the power consumption during normal operation is 4MW.

It can now be said to be AD7441/AD7451, which consumes 4MW in each conversion cycle and lasts 2 μs.

Therefore, the average power consumed in each loop of 100 KSPS is the average power of each cycle,

In order to obtain it under the throughput of 320 KSPS or more The best power performance is recommended to reduce the frequency of the serial clock.

Micro -processor and DSP interface

The serial interface allowable parts on AD7441/AD7451 are directly connected to a series of different microprocessors. This section introduces how to connect AD7441/AD7451 with some more common microcontrollers and DSP serial interface protocols.

AD7441/AD7451 to ADSP-21xx

ADSP-21xx series DSP direct interface with AD7441/AD7451 without any adhesive logic. The setting of the motion control register is as follows:

tfsw rfsw 1 alternate framework

invrfs 1VTFS 1 Activate low frame signal

DTYPE 00 Right -to -Qi Qi

SLEN 1111 16 -bit dataword

ISCLK 1 Internal serial clock

tfsr rfsr 1 Fragment each word

IRFS 0 [0 [0 [0 [ 123]

ITFS 1

In order to achieve the power loss mode, SLEN is set to 1001 to issue an 8 -bit SCLK emergency.

The connection diagram is shown in Figure 33. ADSP-21XX bundle the TFS and RFS of the motion together, the TFS is set to the output, and the RFS is set to input. DSP works in a framework mode, and the motion control register is set according to the instructions. The generated frame synchronization signal TFS is connected to CS, and, like all signal processing applications, is equal samples. However, in this example, the timer interruption is used to control the sampling rate of ADC, and in some cases, equal sampling cannot be achieved.

For example, the timer register loads a value, which provides interruption within the required sampling interval. When receiving interrupts, a value is transmitted with TFS/DT (ADC control word). TFS is used to control RFS to control data reading. The frequency of the serial clock is set in the SCLKDIV register. When using the TFS sending instruction, that is, AX0 TX0, check the status of SCLK. DSP waits for SCLK to become tall, lower, and high before being transmitted. If the selection of the timer and SCLK value makes the instructions to be sent occurred on the rising edge or near the SCLK, the data can be transmitted or waited for the next clock edge.

For example, the main clock frequency of ADSP-2111 is 16MHz. If the SCLKDIV register is loaded at 3, the SCLK of 2 MHz is obtained, and each SCLK cycle passes through the 8 main clock cycle. If the load value of the timer register is 803, the interrupt and the subsequent transmission instructions are issued100.5 SCLK. Because the transmission instruction occurs on the edge of SCLK, this situation causes non -balanced sampling. If the number of SCLK between interruption is an integer, the DSP is implemented by the equal sampling.

AD7441/AD7451 to TMS320C5X/C54X

TMS320C5X/C54X serial interface uses continuous serial clock and frame synchronization signals to synchronize data transmission operations with AD7441/AD7451 and other peripherals Essence CS input allows easy connection between TMS320C5X/C54X and AD7441/AD7451 without any adhesive logic. The serial port of the TMS320C5X/C54X is set to work under the emergencies of the internal CLKX (TX serial clock) and FSX (TX frame synchronization). The serial port control register (SPC) must have the following settings: FO 0, FSM 1, MCM 1, and TXM 1. Format FO can be set to 1, set the length of the word to 8 digits in order to implement the power -off mode on AD7441/AD7451. The connection diagram is shown in. Note that for signal processing applications, frame synchronization signals from TMS320C5X/C54X must provide a spacing sampling.

AD7441/AD7451 to DSP56XXX

The connection diag