Input Return Losses (S11)

Input Return loss is to measure the degree of input impedance (frequency) and source impedance matching. This is a relatively independent gain setting, whether it is non -conversion configuration and reversal configuration. Typical features show the S11 order of Figure 48 and Figure 49 to 1GHz circuit (non-reversible gains are +8 and reverse gains to -8 operations). No reverse operation provides a better matching frequency. The only deviation is due to the parasitic input capacitance of the input pin. Because the amplifier itself shows a very high input impedance, the non -conversion input matching is only set to the ground with the resistance to the non -converted input. The reverse operation is also very good, but the increase rate is faster due to the effects of loop gain attenuation effects in the reverse node. The input of the inverter mode is set up in parallel combination of RG and RT in Figure 49, because the inverter amplifier node can be regarded as virtual ground. A good fixed -gain radio frequency amplifier input voltage residence (vswr) lt; 1.2: 1. This corresponds to S11 of -21 DB. OPA695 surpasses this performance through 100 MMS and 400 MMS non -conversion modes.

Output Return Return List (S22)

The output echo loss is the degree of measuring the output impedance (frequency) and load impedance. This is a relatively independent gain setting, whether it is non -conversion configuration and reversal configuration. The output matching impedance is the first -order, which is set to add a series resistance to the low impedance output of the computing amplifier.

Because the operational amplifier itself shows the low output impedance with the frequency, it can improve the output matching by adding a small balanced capacitor to the output resistor. Typical features show the measured S22, whether or not this 2.5-PF capacitor (through the 50Ω output resistance). Similarly, a good match for a fixed -gain radio frequency amplifier will generate 1.2: 1 resident wave ratio (S22 LT; –21 DB). The typical characteristic curve shows that a simple 50Ω output resistance is kept between-21 and 140 MMS, but it can be maintained by 380 MMS in the case of tuning capacitors.

Positive gain (S21)

In all high -speed amplifiers data tables, positive gain is a small signal gain drawn on the frequency. The difference between non-switching and inverting operations is that the phase of the S21 starts from 0 ° (non-conversion), while -180 ° (reverse). The initial phase shift of this reversal mode is not important for most medium -frequency band applications. The phase of the S21 is not displayed in the typical feature, but it becomes a linear relationship with the frequency, and it can accurately model the time delay by the amplifier.

Typical features show that S21 is within a signal gain range, and the external resistance has been adjusted to re -optimize the flatness of each gain setting. Because this is a current feedback computing amplifier, the expected gain settingWhen changing, the signal bandwidth can remain relatively constant. The relationship between non -conversion bandwidth and gain shows some changes between bandwidth and gain (due to the parasitic capacitor effects on the reverse node), and the changes in the inverter operation mode are very small.

In the calculation amplifier data table, signal gain is usually called V/V. This is the voltage gain from the input to the output, which is set by the external resistance ratio. The impedance of the frequency division is matched by a resistor with a series of resistors, because the output of this resistor is matched by a resistor. Figure 48 The number of pairs of the conversion circuit matching load in China is:

Figure 49 The number of matching loads in the inverter circuit is:

[ [

[ 123]

The specific resistance values u200bu200bused in FIG. 48 and Figure 49 provides the maximum flat bandwidth and 12 DB gains for matching loads. The design tables in the noise coefficient summarize the resistance values u200bu200brequired by the circuit in Figures 48 and Figure 49 within the expected gain range.

As the expected signal gain increases, the achievement can be reduced. Without changing, its decrease is relatively fast, as shown in typical features. The inverse configuration remains almost constant bandwidth (using the correct external resistance value) until the RG decreases to 50Ω, and maintains this value to meet the input impedance matching requirements. In Figure 49, it increases the further increase of RF to achieve further gain. Then the bandwidth decreases rapidly, as shown in the gain chart of -16 V/V in the typical feature.

Reverse isolation (S12)

Reverse isolation is a method of returning source to the power to inject output pins. Because the operational amplifier is almost one -way signal device, it rarely specifies the operational amplifier. Below 300MHz, the non -reversal configuration of FIG. 48 provides a better isolation than the reversal of Figure 49. Through 350 MMS, the isolation of the two is much lower than 40 decibels.

Dynamic range restrictions

The next consideration of the radio frequency amplifier application is the limitation of the dynamic range. Typical fixed gain radiation frequency amplifier includes:

–1-DB compression (measurement of maximum output power)

double tone, third-order, output intermodation intermodation Distance (measurement that can be implemented without any messy dynamic range)

noise coefficient (the amount of signal-to-noise ratio decreases when the amplifier) u200bu200b

-1-DB compression

-1-DB compression power definition is the output power, where the actual power is 1DB smaller than the input power, plus the number of pairs. Among the classic RF amplifiers, this is usually 10 points smaller than the third -order intercept. This relationship does not apply to the computing amplifier, because the loop gain increases the cutting distance by 10 points, which is much higher than the compression of 1 decibel. OPAA simple estimation of the -1-DB compression of 695 is the maximum non-rotating limit output voltage swing available under the matching load, and the power converted to 1DB to meet the definition. For OPA695 on ± 5-V power supply, its output will provide about ± 4.0 V at the output pin or ± 2.0 V under the matching load. From VPP to power conversion (for sine waves) is:

Convert the 4.0-VPP swap time to DBM to get 16 dBM; increased on this basis increase 1 DB (to meet definitions) can compress OPA695 when working at ± 5-V power supply 17 DBM – 1-DB. This is a good estimate for the frequency of full conversion rate below OPA695.

The maximum operating frequency of the available conversion rate and expected peak output (sine wave output pins) is:

will 4600-v The conversion rate of /μs is placed in the reversal operation mode, and the peak output swing at the 4.0-V peak output at the output pin can obtain a maximum frequency of 259 MHz. This is the maximum frequency that matches the -1-DB compression to 17 dBM. At a lower output power, higher available bandwidth is possible, as shown in a large signal bandwidth curve. As shown in the figure, the 7-VPP output at the 100MHz frequency response is almost perfect, whether it is not inverted or inverted.

Double -tone third -order output intermodation (OP3)

In a frequency band in a narrow band, each amplifier usually feeds into a tie filter that can attenuate most of the harmonic. The rest of the most troublesome distortion is the third order, dual -sound interoperability, it can be very close (at the frequency) signal, and cannot be filtered out. If the two test frequencies are defined as FO+ΔF and FO -ΔF, the product of third -order interoperability distortion will be reduced at FO+3ΔF and FO -3ΔF. If the two test power levels (PT) are equal, the OPA695 generates a third -order bandate (PS) at these frequencies, and at the power level below the test power level, the following formulas are given:

The third -order cutter shown in the typical features shows that the cut -off distance at low frequency is very high, and the frequency increases and decreases. This cutter is defined under the matching load to allow direct comparison with the fixed -gain radio frequency amplifier. To generate a 2-VPP full dual-sound envelope under the matching load, each power level must be 4DBM under the matching load (1VPP). The performance curve of Formula 5 and reversal operations, at 50 MHz (41.5 dBM interception), the third -order bandard will be reduced by 2 × 41.5–4) u003d 75 dB compared to these 4dbm test sounds. This is an unusually low distortion for the amplifier with only 13 mAh power current. If the output is directly driven to the ADC inputIn the lighter load, the significant improvement of this performance level is also possible.

This very high interception and static power are achieved by the high -circuit gain of OPA695. However, this loop gain will indeed decrease with the frequency, resulting in the decline in OP3 performance shown in typical features. If the output of the intercepting the amplifier in the case of 200 Mixh is 200 Mikh to 200 Mikh, it will reach 21 Mixh. The interception performance has changed slightly with the gain settings, decreased at a higher gain (that is, the 8 V/V or 12 DB gains used in the typical characteristic curve), increased at low gain.

Noise coefficient

All fixed gain radio frequency amplifiers show a very good noise coefficient (usually lt; 5 dB). For a broadband amplifier, this is achieved by a low noise input transistor and a feedback setting. This feedback greatly reduces the noise coefficient of a fixed -gain radio frequency amplifier, but it also makes the input match depends on the load, and the output match depends on the source impedance of the input terminal.

The noise coefficient of the computing amplifier is always higher than the fixed -gain radio frequency amplifier. This is because the internal circuit of the computing amplifier is more complicated (providing higher input noise voltage and current items). In addition, for a simple circuit, the input matching settings to the resistance. What is obtained is an almost perfect I/O impedance matching, a better load isolation, a very high third -order intercepting phase for static power. If OPA695 has sufficient gain in the IF chain, these higher noise values u200bu200bcan be accepted.

The operating amplifier noise coefficient equation includes at least six items (see noise performance), which is due to external resistance. As a reference point, the circuit in Figure 48 has a 14 dB input noise coefficient, and the anti -phase configuration of Figure 49 has an input noise coefficient of 11 dB. Under a higher gain, the reversal noise coefficient is usually better than the equivalent gain and no reversal configuration. By adding a 1: 2 turning voltage to transformer to the input terminal, the noise coefficient of OPA695's non -reversing structure is increased. This configuration is shown in Figure 52.

The transformer provides a noise -free voltage gain to sacrifice higher source impedance, and for OPA695 no conversion input current noise. The 200Ω resistor on the secondary side of the transformer will still enter the impedance set to 50Ω. A 1: 2 turning transformer will reflect 200Ω as a 50Ω impedance to the input side of the transformer. Use a 1: 2 booster transformer to reduce the gain of the required amplifier by 1/2 to obtain any specific expected overall gain.

Table 1, Table 2, and Table 3 summarizes the recommended resistance values u200bu200band noise value generated by the three circuit options running as a precision medium -frequency amplifier. In each case, RF and RG are adjusted according to the best bandwidth and the required gain.

In all cases, the precise calculation value of the resistance will be displayed; in the application, select the standard resistance value of the value closest to the value in the table.

Device function mode

OPA695 has two functional modes. By applying logic 1 ( gt; 3.3V) to non -prohibited (disabled) pins, you can access the first functional mode. In this mode, the amplifier is fully enabled and will consume 13 mAh power current.

The second function mode is the disabled state. Access disabilities by access to non -disable pins ( lt; 1.8 v). In this mode, the amplifier is completely disabled and only consumes a current of 100 μA.

Application and implementation

Note: The information in the following application chapters is not part of the TI component specification, TI does not guarantee its accuracy or integrity. TI's customers are responsible for determining the applicability of the component. Customers should verify and test their design implementation to confirm the system function.

Application information

Sound surface wave filter buffer

A common requirement of the intermediate frequency band is to use sufficient gain buffer mixed frequency output to restore Insert loss of narrow belt SAW filter. Figure 65 shows a possible configuration of the driving sound surface wave filter. Figure 53 shows the intercept of the 50Ω load. This circuit works under the inverter mode of the voltage gain to -8 V/V. Use the gain setting the resistor to provide a 50Ω input matching. It has feedback for optimization for the maximum bandwidth (700 MHz in this example), and passes the 50Ω of 50Ω. The output resistance enters the matching network at the input end of the SAW filter. If the insertion loss of the sound surface wave filter is 12 decibels, in the passing band of the sound surface wave filter, the 50Ω load of the audible surface wave output terminal (probably the input impedance of the next medium -frequency platter or the mixer) The net gain is 0 decibels. In this application, the OPA695 isolates the impedance of the first mixer from the SAW filter, and provides a very low second and third -order bandic levels in the SAW filter bandwidth. The reverse operation can provide the widest bandwidth, the maximum gain is -12V/V (15.6DB). Undaled operations provide higher bandwidth when the gain setting is higher than this value, but it will also slightly reduce interception and noise coefficient performance.

This vibration buffer large device

OPA695 can also be used to buffer the original vibration (LO) of the bleach. Working at the voltage gain of +2, OPA695 provides a nearly perfect load isolation for Bin Zhen, and the net increase in the hybrid is 0 dB. It can be considered through the application of 1.4GHz service level, but the best operation conditions are service levels lt; 1.0GHz, and the gain is +2. OPA695 is okayProvide gain to drive higher power levels of the mixer. OPA695 as an option for LO buffer is shown in Figure 54. Because OPA695 can drive multiple output loads, two of the same vibration signals can be transmitted to the mixer in the diversity receiver through two series of 50Ω output resistance. The voltage gain of the output pin is+2V/V, and the gain of the mixer is+1V/V (0dB), but it can easily adjust to provide higher gain.

Broadband cable drive application

The high conversion rate and bandwidth of OPA695 can be used to meet the most harsh cable -driven applications.

Cable modem return path drive program

Standard cable modem upstream driver usually requires high power on the bandwidth of 5 MM to 65 trillion, while providing distortion of lt; –50 decibel distortion at the same time Essence Highly integrated solutions (including programming gain levels) often do not meet this goal because high loss from the amplifier output to the line. OPA695 higher gain computing power and extremely high conversion rate provides a low -cost solution for transmitting the signal with the required unscrupulous dynamic range. Figure 55 shows an example of the upstream driver using OPA695 as a cable modem return path. In this case, the input impedance of the driver is set to 75Ω from the gain resistance (RG). The input level required for the adjustable incremental level is significantly reduced by the 15.5DB gain provided by OPA695. In this example, the physical 75Ω output matches the resistance, together with the 3DB loss in the dual -device, the output swing amplitude is attenuated by 9 dB on the line. In this example, a single+12-V power supply is used to achieve the 6-VPP output pin voltage through the minimum harmonic distortion of 65MHz. In this example, for the 6-VPP output pin voltage, the measurement performance was obtained through the 65MHz small signal bandwidth and lt; -54dbc distortion.

Another option of this circuit is to use the differential drives of two OPA695S drive output transformers. This can be used to double the power of the available line, or improve the distortion by halving the output required at each stage. Channel disables required by the MCNS specification must be achieved by using the PGA disable function. MCNS disable specifications Requirements to maintain output impedance matching when the signal channel is closed. The disabled features of OPA695 are mainly used for energy saving, and put the output and inverter input pins in high impedance mode. This cannot maintain the required output impedance matching. Turn off the signal at the input terminal of FIG. 55, while maintaining OPA695 activation, maintaining impedance matching, and making the noise on the line very small. Due to the low input noise of OPA695, the circuit 55 circuit (PGA source is closed, but still presents 75Ω source impedance) will be very low 4 nv/√Hz (–157 dbm/hz).

RGB video line driver

OPA695's extremely high band width operation at a +2 gain, supports the fastest RAMDAC output such as auxiliary monitor drivers and other applications Essence The gain 2V/V video cable driver shows the measurement performance of 0 →+1V at 125MHz. Generally speaking, the full power bandwidth required for the amplifier must be at least half of the pixel rate. OPA695's non -ease gain is +2, the conversion rate is 2900V/μs, and the output pins voltage of the standard RGB video level is 1.4VPP, the bandwidth is 600MHz, which can support pixel rates up to 1.26GHz. Figure 56 shows an example. Three OPA695 provides auxiliary monitor output for high -resolution RGB RAMDAC.

From a video conversion circuit with a high conversion rate, from a higher bandwidth to a high -bandwidth video conversion circuit. This will provide a clearer pixel edge than the circuit in Figure 56. Most high -speed digital modular converters are current control design, which have both the output current signal used for video, as well as a complementary output that is usually discarded in the matching resistor. The complementary current output can be used as auxiliary output, if it is reverse, as shown in Figure 57. In the circuit in FIG. 57, a complementary current output is connected to an equivalent 75Ω impedance (parallel combination of RT and RG), which also provides a current segmentation to reduce the signal current of the feedback resistor RF. This allows RF to increase to the value that maintains a flat frequency response. Since the complementary current output is basically an reverse video signal, the circuit sets a white video level at the output terminal of OPA695 for zero DAC output current (using 0.77 volt DC partial pressure on the non -turquate input terminal), and then reverse the reversal A complementary output current to generate a signal of 0 volts from 1.4 volt from zero -output current to a 0 volt of the maximum output current (assuming the maximum output current is 20 mAh). This provides a very broadband ( gt; 800 MMS) video signal ability.

Any waveform drive

OPA695 can be used as an output stage for the application of any waveform drive application. When the OPA695 is operated on the ± 5 V power supply, it can be driven to the 50Ω matching load through a 50Ω series matching resistor, and it can achieve a swing of up to 4.0-VPP under the matching load (15 dBM). This power level can be used for gain to ± 8, and a 100 MHz flat response. When the DAC interface is directly output from the complementary current, the circuit in Figure 57 is considered, and the circuit is modified for the peak output current of the specific DAC considers. If the pure AC coupling output signal from the complementary current output DAC is needed, consider using the push output stage of the circuit 58 circuit. The resistance here is 20 mThe calculation of the An Peak output current DAC will generate up to 5-VPP swing under the matching load (18 dBM). This method provides higher power under the load, and has lower second harmonic distortion.

For the 20 mAh peak output current DAC, due to the ground ground resistance of the output terminal, the 10 mAh mid -standard current provides a 2 -volt DC output co -mode working voltage. The total AC impedance of each output end is 50Ω, and the 2-V co-mode voltage of DAC generates ± 0.5-V swing around. These resistors also serve as current distributors, sending 75%DAC output current through feedback resistors (464Ω). The blocking capacitor connects the output voltage of the OPA695 and converts the single DAC output current to 0.75 × 20mA × 464Ω u003d 7VPP at each amplifier output place. Each output is exactly 180 ° from the other output, and two 7VPPs are generated into the matching resistor. In order to limit the peak output current and improve distortion, the circuit of FIG. 58 set up a 1.4: 1 antihypertensive transformer. This reflects the 50Ω load of the transformer on the side of 100Ω. For the maximum 14-VPP swing of the two amplifiers output, the matching resistor will reduce it to 7VPP at the transformer input terminal, and then the 50Ω load at the transformer output will drop to the maximum 5-VPP. This lowering method reduces the peak output current to 14VP/(200Ω) u003d 70mA.

Differential I/O Application

OPA695 provides a very low third -order distortion item. For single -player operation, it has the main second -order second -order operation distortion. For the lowest distortion, especially when the difference is required, operating two OPA695s in the design of the differential I/O design can inhibit these even -order items, and provide extremely low harmonic distortion through high frequency and high power. Differential output is usually the first choice for high -performance ADC, twisted tie drivers and mixer interfaces. The two basic methods of implementing differential I/O are no reversal or reversal configuration. Because the output is different, the polarity of the signal is a bit meaningless; the ""non -reverse"" and ""reverse"" term here are suitable for the situation where the input is brought to the two OPA695s. Each method has its advantages and disadvantages. Figure 59 shows the basic starting point of non -reversing gauge I/O applications.

This method allows the source end impedance to independent signal gain. For example, a simple differential filter can include in the signal path until non -reversing input, not interacting with gain. Figure 59 Differential signal gain is:

Since OPA695 is a current feedback amplifier, its bandwidth is mainly controlled by feedback resistance: Figure 59 shows a typical value of 500Ω. However, only the RG resistance can adjust the difference in differences with considerable freedom. RG canTherefore, it provides a non -meritorious network of isolation and plastic surgery for the difference frequency response. AC coupling applications usually include blocking capacitors connected in series with RG. This will reduce the gain to 1 at low frequencies and increase at a higher frequency to the AD expression shown above. The non -reversing input method in Figure 59 can be used to gain higher than the reversal input method, but because the conversion rate of OPA695 in non -reversing input and reversal input mode is low, it may have a lower full power bandwidth width. Essence

Various combinations of single power supply or AC coupling gain can also be implemented using the basic circuit of Figure 59. Two non -ease input bias bias voltage is transmitted to the output terminal at the gain of 1, because the equal DC voltage at each inverter node will not generate an current through RG. The circuit shows the co -mode gain from the input to the output to 1. If it is not necessary (input transformer), the power connection must be removed by the co -mode signal, or the co -mode voltage of the input terminal can be set to the output co -mode bias. If the low co -mode inhibition of the circuit is a problem, the output interface can also be used to suppress the co -mode. For example, most modern differential input ADC can well suppress the co -mode signal well, and the line drive application of the transformer can also eliminate the co -mode signal of the secondary side of the transformer.

FIG. 60 shows the differential I/O of the inverter amplifier. In this case, gain resistance (RG) becomes part of the power input resistance. This provides a better noise performance than non -reversal configuration, but limits the flexibility of separating the input impedance from the gain.

These two non -conversion inputs provide a simple co -mode control input, especially if the power supply is coupling through a block or a transformer. In any case, the two non -converted input -end input voltage on the output end is 1, thereby providing simple co -mode control for the single power operation. The OPA695 in this configuration will be limited to the 500Ω area to obtain the best frequency response. In the case of RF fixed, the input resistance can be adjusted to the required gain, but it will also change the input impedance. The high -frequency co -mode gain from the input to the output is the same as the signal gain. Similarly, if the source may include a co -mode signal that does not want, you can use blocking caps (for low -frequency and DC co -mode) or transformers on the input terminal to reject the signal. The differential performance diagram displayed in the typical feature uses the configuration and input 1: 1 transformer of FIG. 60. The difference between the differential signal gain in Figure 60 is:

Using this configuration can inhibit the second harmonic, leaving only three harmonics as a limit for output SFDR. The high conversion rate of the inverse configuration also extended the range of full power bandwidth and low interoperability distortion, exceeding the performance bandwidth of the circuit available in Figure 59. Typical features show that the circuit of FIG. 60 works at AD u003d 10, which can transmit a signal with a signal of more than 16 VPP 500 MHz – 3 DB bandwidth. Use Formula 4, which meansThe differential output of each output is converted to 18000 V/μs, or 9000 V/μs. This output conversion rate is much higher than the specified value, which may be due to the mild load used in the differential test.

This reverse input difference configuration is suitable for high SFDR converter interfaces, especially the narrow band intermediate frequency channel. Typical features show that within the range of 90MHz, the two -tone and 3 -order interoperability exceeding 45dbm. Although these data are collected under the 800Ω load, the interception model seems to be applicable to the circuit, which regards the power level as 50Ω. For example, at 70 MMS, the typical feature map of the differential shows the cutting distance of 48 dBM. In order to predict the 2-sound interoperability SFDR, assuming that the maximum differential input converter of the 2-VPP is lower than the full marking package -1-DB, the test power level of each tone will be 9 dbm – 6 dbm u003d 3 dbm. Put it into the intercept equation and get:

Single distortion data shows that when 70 MHz is output to 800Ω load, the SFDR is about 72 DB. A moderate rear filter behind the amplifier can reduce these harmonics (the second time is 140 MM, the third time is 210 MHH) to a point. In a 70 trillion -meter intermediate frequency operation, the full SFDR of the converter can be at 85 at 85 Within a decibel range.

Operation suggestion

Set the resistance value to optimize the bandwidth

current feedback computing amplifier, such as OPA695, can maintain almost constant bandwidth exceeding the signal gain settings and appropriate adjustment external resistance. value. This is manifested in typical features. With the increase of small signal bandwidth, the gain has decreased slightly. These curves also show that the feedback resistance has changed each gain settings. The resistance value of the current feedback computing amplifier circuit can be regarded as a frequency response compensation element, and their ratio determines the signal gain. Figure 15 shows the OPA695 small signal frequency response analysis circuit.

The key element of this current feedback computing amplifier model is:

α #8658; from non -reverse input to reversal input buffer gain.

ri #8658; buffer output impedance

Ierr #8658; Feedback error current signal

z (s) #8658; The frequency of IERR to VO is related to the open -loop cross -resistant gain

The buffer gain is usually very close to 1.00, and it is usually ignored from the signal gain consideration. However, it will set CMRR for a single computing amplifier differential amplifier. For buffer gain lt; 1.0, cmrr u003d --20 × log (1 –α).

Caps output impedance RI is a key part of the bandwidth control equation. For OPA695, for ± 5-v operation, its typical value is about 28Ω, and for single+5-v operations, it is usually 31Ω.

The current feedback operation amplifier sensor sensor's error current in the anti -phase node (the difference in input error voltage of the voltage feedback computing amplifier is contrary to the voltage feedback computing amplifier), and passes it to the output through a cross -resistant gain related to the internal frequency. Typical features indicate such an open -loop cross -block response. This is similar to the opening voltage gain curve of the voltage feedback computing amplifier. Development Figure 64 circuit tran