Features

■ Two operations with synchronous rectifier control

■ Super fast load transient response

■ Integrated large current grid polar driver: up to 2A grids Current

■ 3 -bit programmable output or external reference with 0.900V to 3.300V.

± 0.9%output voltage accuracy

■ 3MA available for reference

■ Integrated programmable remote controllers

123] ■ 10%contribution accuracy

■ Digital 2048 Step Step Soft Starts

■ Prying pole lock over voltage protection.

■ Non -closed lock -ups.

■ Use the lower MOSFET RDSON or induction resistor to achieve over -current protection

■ oscillator outer adjustment, internal fixing at 150kHz

■ Good output and inhibitory functions

■ Packaging: SO-28 and VFQFPN-36

Application

■ Large current DC/DC converter

■ distributed power supply

The block diagram

Instructions This device implements a double -phase antihypertensive controller, each each, each, each, each, each, each, each, each, each of which implements a double -phase antihypertensive controller, each of which The phase offset between the phase is 180, which is optimized for the application of large current DC/DC.

The output voltage can be programmed by integrated DAC from 0.900V to 3.300V; programming 111 code, using an external reference voltage from 0.800V to 3.300V for adjustment.

A programmable remote control amplifier avoids the use of external resistance division and restore losses on the distribution line.

This device ensures fast protective load current and over/undervoltage voltage. If the voltage is detected, the internal pry rod is provided to open the low -voltage side MOSFET.

The output current is limited in the constant current mode: When the underwriting is detected, the device is reset and the operation is restarted.

Reference diagram

Device description

This device is an integrated circuit implemented by BCD technology. It provides complete control logic and protection for high -performance double -phase antihypertensive converters, and optimizes large current DC/DC applications. It is designed as a n -channel MOSFET in a two -phase synchronous rectification buck topology. Provide 180 degrees of phase shift between the two phases, allowing reducing the input capacitor current ripples while reducing the size and loss. The output voltage of the converter can be accurately adjusted, programmable VID pins, the range is 0.900 to 3.300V, the maximum tolerance of temperature and wire voltage changes is ± 0.9%. The programmable remote control amplifier avoids the use of the external resistor division, allowing the voltage drop on the distribution line, and the output voltage can be adjusted to the different values of the available reference value. The device provides average current mode control and fast transient response. It includes a 150kHz free -run oscillator, which can be adjusted by the resistor. The error amplifier has a conversion rate of 15V/μs, allowing high converters to achieve fast transient performance. The current information is read through the lower MOSFETS RDSON or the LS-MOS sensor of the LS-MOS in a full differential mode. Current information correction PWM output to balance the average current of each phase. Under static and dynamic conditions, the current between the two phases is limited to ± 10%, unless the expansion of the sensing element is considered. The drooping effect is programmable to minimize the output filter and load transient response: This function can be disabled, and the current information available on the pin can be used for other purposes. This device prevents over current, and each phase has an OC threshold to enter the constant current mode. Because the current is read through the low side MOSFET, the device keeps the current triangular waveform at the bottom of the inductor constant. When the underwriting is detected, the device is reset, all MOSFETs are closed, and then the suddenly restarts. The device also performs a prying rod overvoltage protection, and immediately locks the operation to open the lower driver and the driver's high fault pins.

oscillator

The internal fixation of the switching frequency is fixed at 150kHz. Each phase works at a fixed frequency of an oscillator, so that the switching frequency generated on the load side will double.

The internal oscillator produces triangular waveforms for PWM charging and discharging through internal capacitors. The current transmitted to an oscillator is usually 25 μA (FSW 150kHz), and it can be changed using an external resistor (ROSC) connected to the osc pin and SGND or VCC. Because the OSC pin is maintained at a fixed voltage (typical. 1.237V), considering the internal gain of 6kHz/μA, the current of the frequency and the pins (pressing) into a proportional change.

Especially when connecting it to SGND, the frequency increases (the current sinks from the pins), and when the ROSC is connected to VCC 12V, the frequency is reduced (the current is forced into the pins), the specifics are specific, and the specifics are specific. As follows:

After pressing 25 μA into the foot, because there is no current to the oscillator, the device stops switching.

Figure 1: ROSC and Switch F

digital mode converter and benchmark

built -in digital modular converter allows the output voltage Adjust from 0.900V to 3.300V, as shown in Figure 2. You only need to change as a remote amplifier in the resistor division, and you can reach different voltages (see the relevant chapterFestival).

Internal benchmarks are adjusted during the production process, the output voltage accuracy is ± 0.9%, and the zero temperature coefficient is about 70 ° C. It also includes error amplifier offset compensation. It is programmed by voltage recognition (VID) pin. These are the input of internal DACs that provide the resistance of the internal voltage benchmark partition through a series of resistance. VID code drives a multi -way relicant, which selects a voltage at the precise point of the pressure division (see Figure 2). DAC output is transmitted to an amplifier that obtains VPROG reference voltage (that is, the setting value of the error amplifier). Provides internal pulling (with a 5 μA current generator, the typical value is 3V); in this way, when the programming logic 1 , you only need to float the pin, and SGND.

该装置提供一个双向引脚REF_IN/OUT：用于调节的内部基准通常在该引脚上可用，具有3mA的最大电流容量，但当编程VID代码111时除外；在这种In the case, the device receives external reference and adjusts it through the Ref_IN/OUUT pin. When using external benchmarks, the range must be from 0.800V to 3.300V to ensure the normal function of the equipment.

FIG. 2 shows a frame diagram of how to manage regulations when using internal or external references.

Voltage recognition (VID) pin configuration or external reference provided also sets the PowerGood threshold (PGOOD) and overvoltage/OVP/UVP threshold.

Figure 2: Reference Management

Output stabilization accuracy can be extracted from the following relationship (in the worst case):

]

(the worst situation of internal reference)

(the worst situation of external reference)

Among them, VOS_RA The offset related to the Vos_ea is related to the error amplifier and the remote amplifier. KOS 1+1/RA_ gain reflects the impact of remote amplifier gain (RA_ gain) on adjustment (see related chapters).

Statistical analysis can consider using a square root method (RSS) calculation accuracy, because all variables are statistically independent, as shown below:

(internal internal Reference)

(with external reference)

The driver's room

Integrated large current drive allows different types of power MOS (also You can use multiple MOS to reduce RDSON) to keep the switch conversion quickly.

The driver of the high -voltage side MOSFET uses Bootx pin to power, PHASEX pin is used to return. The low -end MOSFET driver uses VCCDR pins to supply power, and PGND pins are used for circuit. The minimum voltage of the VCCDR pin is 4.6V to start the operation of the device.

The controller contains a complex anti -cutting system to minimize the conduction time of the low -side diode, maintain good efficiency, and save the use of the Schottky diode. The time of the dead area is reduced to a few nail seconds to ensure that the high -voltage and low -voltage side MOSFET will never be turned on at the same time: when the high -voltage side MOSFET is closed, the voltage on its source starts to decrease; when the voltage reaches 2V, the low side MOSFET gate driver is driven Delayed by 30ns. When the low side MOSFET is closed, the voltage on the LGATEX pin is detected. When the voltage drops below 1V, the high side MOSFET gate driver uses 30ns delay. If the current in the inductor is negative, the source of the high side MOSFET will never decrease. Even in this case, in order to allow the low -side MOSFET to open, a watch dog controller is enabled: if the source of the high side MOSFET does not drop by more than 240ns, the low -side MOSFET is opened, which allows the negative current of the inductance to circulate. Even if the current is negative, this mechanism allows the system to adjust.

Bootx and VCCDR pins are separated from the power supply (VCC pins) of IC (VCC pins) and signal grounding (SGND pins) and power grounding (PGND pins) to maximize the switching and antipity. The independent power supply of different drivers provides a high flexibility for the choice of MOSFET, allowing MOSFETs with logic levels. You can choose several power combinations to optimize the performance and efficiency of the application. The power conversion is flexible, and the 5V or 12V bus can choose freely.

FIG. 3 shows the peak current of the upper drives and the lower drive of the two phases. 10NF capacitance load has been used. For the upper-layer drive, the source current is 1.9A, and the trap current is 1.5A, and the VBOOT-V phase 12V; similarly, for the lower drive, the source current is 2.4A, while the sinking current is 2A, VCCDR 12V.

FIG. 3: Driver Peak current: High -voltage side (left) and low -voltage side (right)

current readings and overcathered

The voltage of the sensing resistance (RSENSE) of LS-MOSFET through the low-side MOSFETS RDSON is reduced to read the current through the current and converts the current into an current. The cross -guidance ratio was issued by the external resistor RG where the chip was placed between the isenX and the PGNDSX pins. Differential current reads can inhibit noise and allow sensor elements to place sensor elements in different positions without affecting the measurement accuracy. The current reading circuit reads the current during the low side MOSFET opening (closing time). During this period, the reaction makes the pinch isenX and PGNDSX remain in the same voltage, and within the time of the closing of the read circuit, the internal clamping to keep these two pins in the same voltage, from the current of the IsenX pin sinking RDSON Sense to avoid absolute maximum rated value overcoming ON, you need) Isenx pin).

Patented current reading circuit allows very accurate and high -bandwidth positive and negative current readings. The circuit uses a high -speed tracking to keep the transgender amplifier reproduce the current of the sensing element. In particular, it reads the current in the second half of the closing time to reduce the noise injected into the device due to MOSFET lead (see Figure 4- left). The tracking time must be at least 200ns in order to correctly read the transmitted current.

The circuit provides a constant 50 μA current from the PGNDSX pin: it must be connected to the ground side of the sensor element through the RG resistor (see Figure 4- right). The two current reading circuit uses this pin as a reference to keep the IsenX pin at this voltage.

The current in the Isenx pin can be concluded by the following formulas:

Among them, RSENSE is an external sensing resistance or low -end MOSFET, RDSON, and low -end MOSFET. RG is a cross -direction resistance used between IsenX and PGNDSX pins towards the reading points; iPhasex is a relatively phase -carried current. The internal reappearance of the current information is expressed by the second item of the previous formula, as shown below:

Since the current is read in the differential mode, the negative current is The information will also be retained; this allows the device to check the dangerous return current between the two phases to ensure the complete equilibrium between the phase current. According to the current information of each phase, take the total current (IFB IINFO1+IINFO2) and the average current of each phase (IAVG (IInfo1+Iinfo2)/2). IINFOX is then compared with IAVG to correct the PWM output to balance the current carried by the two phases.

FIG. 4: The current readings of the current (left) and the circuit (right)

Cross -resistant resistor RG can be designed as per phase of each phase under a full rated load. With 25 μA current information; over -current intervention threshold settings are set to 140%(IInfox 35μA) of the nominal value.

According to the above relationship, the over -current threshold (IOCPX) of each phase must be set to 1/2 of the total transport maximum current, and the result:

When the current is the current When the bottom of a current influenza component, the current responds to a current with a current greater than the current.

■

l6712

-D dynamic maximum duty cycle limit

maximum duty cycleThe function that is limited to the measurement current is fixed because the frequency of the oscillator is fixed after programming, which means that the maximum connection time limit is as follows (where T is the switch cycle T 1/fsw, iOUT is the output current):

[[[[[

123]

This linear relationship is 0.80 · t under zero negative load, and at the maximum current of 0.40 · t, it is a typical value, which causes two different behaviors of the device:

] Figure 5: ton restriction operation

1.T limit output voltage.

This is the case when the current reaches the maximum connection time when the current reaches the maximum connection time of the IOCPX (infox u0026 lt; 35μA).

FIG. 5A shows the maximum output voltage that can be adjusted to adjust the ton restrictions applied by the previous relationship. If the expected output characteristics exceed the maximum output voltage, the output voltage will begin to decrease after leap. In this case, the device does not perform constant current restrictions, but only limits the maximum duty cycle according to the previous relationship. The output voltage follows the characteristics generated (as shown in Figure 5b) until the UVP is detected, or until IFB 70 μA.

2. Constant running

When the current of each phase reaches the connection time limit when the current reaches the IOCPX (IInfox u0026 GT; 35μA), this will occur.

The device enters the quasi -constant current operation: The low -side MOSFET is kept on, until the current reading is lower than the IOCPX (IInfox u0026 LT; 35μA), and the clock cycle is skipped. In the next available clock cycle, the high side MOSFET can be turned on by the control loop to apply a ton of voltage, and the device works in a normal way before detecting another OCP event.

This means that under overcurrent, the average current will increase slightly due to the increase in current ripples. In fact, because the current must reach the bottom of the IOCPX, the increase in the interruption time will lead to an increase in connection time. The worst case is when the connection time reaches the maximum value.

When this happens, the device works in the constant current, and the output voltage decreases as the load increases. More than the UVP threshold will cause device reset.

FIG. 6 shows this working state.

You can observe the peak current (IPEAK) greater than IOCPX, but you can determine as follows:

Among them Show).

The device works under constant stream, and the output voltage decreases with the increase of the load until the output voltage reaches the underwriting threshold (Voutmin).

The maximum average current result of the constant stream is:

In this special case, the result of the switching frequency is reduced. Opening time is the maximum value (TONMAX), and the closing time depends on the application:

Figure 6: Hengli operation

]

When the Iinfox reaches 35 μA (if B 70 μA), the current is still set. Full load value is just a convention, which is used to handle the convenience value of IFB. Because the OCP intervention threshold is fixed, in order to modify the percentage of the load value, it can be simply believed that, for example, set the OCP threshold to 200%, which will correspond to infox 35μA (IFB 70 μA). The full load current will correspond to iinfox 17.5μA (if B 35μA).

Once the UVP threshold is intercepted, the device will be reset without the turnover of all power MOSFETs. Then perform another soft startup, allowing the device to recover from OCP after eliminating the overload cause.

Excellent UVP threshold will cause device reset: Close all MOSFETs, and then implement new soft startup, allowing the device to recover after the overload cause is eliminated.

■

l6712a

-The fixed maximum duty cycle limit

The maximum duty cycle is fixed and keeps constant with the current current. Once the OCP threshold is overcome, the device will run in a constant current. Refer to the above -mentioned constant stream parts, only the different values under the maximum load are required, as shown below:

The above relationship about the one -time delivery of the quasi -constant stream and the constant current can be delivered at one time The formula is still effective in this case.

Remote testing of a large meter

The remote control amplifier is integrated in order to recover from the losses in the PCB line and wiring. To maintain adjustment accuracy. The integrated amplifier is a low offset error amplifier; as shown in Figure 7, an external resistor is required to achieve the differential remote test.

Figure 7: Remote control amplifier connection

Equal resistance to the generated amplifier's unit gain: programming benchmark will be adjusted in remote load.

In order to regulate the output voltage that is different from the available reference value, the gain of the remote amplifier can be adjusted by changing the value of the external resistor, as shown below (see Figure 7):

[ 123]

In order to regulate twice the reference voltage, the gain of the above report must be equal to u0026#189;.

Modify the gain of the remote amplifier (especially when the value is greater than 1), which can also adjust the voltage below the programming reference value.

Because the amplifier is connected as a differential amplifier, inWhen calculating the offset introduced in the output voltage, the offset of the amplifier must be multiplied by the term KOS [1+(1/ra_gain)], because the voltage generator insisted on non -inverse input voltage generator represents offset amount Essence

If you do not need remote detection, it is enough to connect the RFB directly to the adjustment voltage: VSEN is no longer connected, and it still has a remote amplifier sensor sensor output voltage. In this case, you can choose to use the external resistor R1 and R2, and simply connect the remote control amplifier into buffer to keep VSEN in the prescribed voltage (see Figure 7). Avoid using remote amplifiers to save offset in accuracy calculation, but remote sensing is not allowed.

Integrated speed reduction function (optional)

The dependence between regulating voltage and output current (load adjustment) between the speed reduction function. In this way, part of the output capacitance ESR during the load transition process is restored. As shown in Figure 8, there is an ESR drop in any circumstances, but the total deviation of the output voltage has the least bias.

Connect the sagging pipe foot with FB feet, forced current IDROOP, proportions to the output current, enter the feedback resistor RFB to achieve load adjustment dependencies. If RA_GAIN is a remote amplifier gain, the output characteristics are given by the following relationship (when the speed is enabled):

When the gain of the remote amplifier is 1/2, The adjustment output voltage will be doubled.

During the nominal full load, the drooping current is equal to 50 μA, and 70 μA is equal to the OC intervention threshold. Therefore, the maximum output voltage deviation is equal to:

The speed reduction function is only suitable for positive loads; if the negative load is applied and then IInfox u0026 LT; 0, the FB pin does not sink the current. The device is adjusted under the voltage of VID programming.

If this effect is not required, the short circuit of the drooping foot to SGND will be adjusted as the voltage mode buck converter.

Figure 8: The load transient response (left) and the drooping foot connection (right).

Monitoring and protection

This device monitors the voltage through pins vSEN to establish a good signal and manage OVP/UVP status.

■ Good: If the voltage that VSEN senses is not within the range of ± 12%(typical values) of the programming value (RA_GAIN 1), the power output is compulsory to low. It is an output of a drain opening, and it is enabled only after the soft start (2048 clock cycle). During the soft start, the pin was forced to be low.

■ UV radiation: If the output voltage monitored by VSEN is lower than the reference in one clock cycleAt 60%of the voltage, the device will turn off all MOSFETs, and reset the operation with a new soft start -up phase (HICCUP mode, see Figure 9).

■ OVP: Once the VCC exceeds the opening threshold, enable: When the voltage monitored by VSEN reaches 115%(minimum value) of the programming voltage (or external reference voltage), the controller opens the two low sides permanently. MOSFET and close two high -sides MOSFET to protect the load. OSC/fault pins are driven by high levels (5V), and need to turn off and turn on the power (VCC) to restart the operation.

Overvoltage and under voltage are also activated during soft start (below the reference voltage 0.6V). In this case, the benchmark used to determine the ultraviolet threshold is an increased voltage driven by 2048 soft startup digital counter, and the benchmark for the OV threshold is the final benchmark or Ref_in/OUT pin that is programmed by the VID tube foot. The benchmark.

Figure 9: UV protection and snoring mode.

Soft start and suppression

When starting, a slope will be generated, which increases the circuit reference voltage from 0V to VID to the 2048 clock cycle programming The final value, as shown in Figure 10.

Once the soft start, the reference value increases: the up and down MOSFET starts the switch, and the output voltage begins to increase with the closed loop adjustment. At the end of the number soft start, the good power comparator was enabled, and then the PGOOD signal was driven by high levels (see Figure 10).

When the increased reference voltage reaches 0.6V, the owed voltage comparator is enabled, and the OVP comparator is always activated. The threshold is equal to the+15%_min of the final reference voltage.

If the VCC and VCCDR pins do not exceed their respective opening thresholds, the soft start will not occur.

During the normal operation, if any underwriting voltage was detected on one of the two power supply, the device was closed. The voltage of the forced OSC/InH pin is lower than 0.5V (typical value) to fail the device: all power MOSFETs and protective devices will be closed until the conditions are eliminated.

Figure 10: Soft start.

Input a capacitor

The design of the input capacitor mainly considers the input average square current, which depends on the duty cycle reported in Figure 11. Considering the two -phase topological structure, compared with single -phase operation, the input -input square root current is greatly reduced.

It can be observed that in the worst case of d 0.25 and d 0.75, the input RMS value is half of the input current of the single -phase equivalent. The power consumption of input capacitance is equal to:

The design of the input capacitor is to maintain the most relative to the most comparedThe ripple of the big load occupies the duty ratio. In order to achieve the required square root value and minimize the cost of the component, the input capacitance is achieved by multiple physical capacitors. The equivalent square -meter root current is the sum of the balance of the equity of a single capacitor.

During the switching process, the capacitors and drain containers must be evenly distributed as possible at the high drain input end to reduce the noise of the MOS input terminal as much as possible. Ceramic capacitors can also introduce the advantages of high -frequency noise decoupling, noise generated by parasitic components along the power path.

FIG. 11: The input average root current and duty -occupying ratio (d) and driving are input.

Output capacitor

The output capacitor is the basic component of the rapid response of the power supply.

Due to the faster load transient response (double the frequency of the switching at the load connection), the two -phase topology reduces the required output capacity. Due to the 180 ° phase shift between the two phases, the elimination of the current ripple also reduces the requirements for the output ESR to maintain the specified voltage ripple.

In addition, if the speed reduction function is enabled, a larger ESR can be used to maintain the same transient tolerance. In fact, when the load transmitted to the output of the converter, the load current is provided by the output capacitor within the initial a few micro seconds. The controller can immediately identify the load transient and increase the duty ratio, but the current slope is limited by electrical value.

Due to the changes in the current in the capacitor, the output voltage decreased for the first time (ignored the impact of ESL):

The smallest capacitor value is maintained without discharge. The output voltage of the capacitor is concluded from the following formula:

Among them, DMAX is the maximum duty cycle. The lower the ESR value, the lower the output voltage of the load transient, and the lower the static ripple of the output voltage.

inductor design

The inductance value is defined by the compromise between time, efficiency, cost, and size. The inductor must be calculated to maintain the output and input voltage changes to keep the ripple current u0026#8710; IL keep between 20%and 30%of the maximum output current. The inductance value can be calculated in this relationship:

Among them, FSW is the switching frequency, VIN is the input voltage, and VOUT is the output voltage.

Increasing the electrical value will reduce the ripple current, but it will also shorten the response time of the converter to the load transient. The response time is the time required to change the current from the initial value to the final value. Since the inductor has not completed the charging time, the output current is provided by the output capacitor. The minimum response time can minimize the required output capacitance.

The response time of the load transient state is different due to the application of the load: if the load is applied,The inductor is equal to the voltage of the input and output voltage difference, and during the removal process, only the output voltage is discharged. The following expression gives the compensation network response enough time u0026#8710; i load transient approximate response time:

The worst case depends on the available input voltage And the selected output voltage. In any case, the worst situation is the response time after the load removed. The minimum output voltage has been programmed and the maximum input voltage is available.

Main control circuit

System control circuit topology depends on drooping pinch connection: if it is connected to FB (speed reduction function activation), the average current mode is considered to be considered, and if it is connected to GND (The drooping function is not activated), the voltage mode must be considered.

In short, the system control circuit closed the average flow control loop to allow the current of the inductors to be appropriately shar