Features

Micro -power operation: 5 V VDD is 950 μA

2.7 V to +5.5 V simulation power supply

16 -bit monotonous

Sinking time: 10 μs to ± 0.003%fsr

I2C #8482; interface is as high as 3.4 Mbps

data transmission capacity

Double buffer input register

up to 16

DAC8574

Synchronous updates supporting up to 64 channels

running at -40 ° C to 105 ° C

Small 16 lead tssop package

process control [ 123]

Data acquisition system

closed -loop server control

PC peripheral equipment

portable instrument

Explanation

DAC8574 is a low -power, four -channel, 16 -bit buffer voltage output DAC. The precision output amplifier on its piece can achieve rail pairing output swing. DAC8574 uses I2C compatible dual -line serial interfaces and supports high -speed interface mode. It supports up to 16 DAC8574, which is used for a total of 64 channels on the bus.

DAC8574 requires external reference voltage to set the output range of DAC. DAC8574 contains a power -on reset circuit to ensure that the DAC output is powered on at zero, and keeps there until the device is effectively written. DAC8574 contains a power -off function that can be accessed by internal control registers. This function can reduce the current consumption of the current of 200NA devices at 5V.

The low power consumption of this component at normal operation is very suitable for portable battery power supply equipment. When VDD 5V, the power consumption is less than 5MW, and the power -off mode drops to 1 μW.

DAC8574 has 16 lead TSSOP packaging.

This integrated circuit will be damaged by electrostatic discharge. Texas Instrument Company recommends that appropriate preventive measures are taken when dealing with all integrated circuits. Not observing the correct operation and installation procedures may cause damage.

The range of ESD damage drops from fine performance to complete equipment failure. The precision setting circuit may be more vulnerable to damage, because very small parameter changes may cause the device to not comply with the specifications it announced.

Packaging/ordering information

Typical features

TA +25 ° C, unless there is another explanation.

] Operation theory D/A Part The architecture of DAC8574 consists of a string DAC and an output buffer. Figure 45 shows the universal box diagram of the DAC architecture. The input encoding of DAC8574 is a non -symbol binary, and its ideal output voltage is:

where d loaded to loading to the load The decimal value of the binary code of the DAC register; its range from 0 to 65535.

resistance string

FIG. 46 shows the resistor group. It is basically a resistor divided by 2, a resistance string behind, and each resistance value is R. The code loaded to the DAC register is to determine which node on the serial of the series to determine which node is distributed to the output amplifier. Because the structure is composed of a string of resistors, it is specified as monotonous.

Output amplifier

Output buffer is a non -easy amplifier with a gain of 2, which can generate rail voltage on its output. The range is 0V to VDD. It can drive the load of 2 k and connect with 1000 PF to the source and exchange power of the output amplifier in the typical curve. The conversion rate is 1V/μs, the half -scale stability time is 8 μs, and the output is empty.

I2C interface

In January 2000, the serial interface developed by Philips I2C bus (see I2C bus specification). The bus consists of a data cable (SDA) with a pull -up structure and a clock line (SCL). When the bus is free, both SDA and SCL lines are pulled up. All device compatible with I2C is connected to the I2C bus by leaking I/O pins, SDA and SCL. The main device is usually a microcontroller or a digital signal processor to control the bus. The host is responsible for generating SCL signals and device addresses. The host also generates specific conditions that indicate the start and stop of the data transmission. Receive and/or send data from the bus under the control of the device under the control of the main deviceEssence

DAC8574 is the following data transmission modes defined in the I2C bus specification: standard mode (100 kbps), fast mode (400 kbps) and high -speed mode (3.4 Mbps). The data transmission protocols in the standard mode and the fast mode are exactly the same, so they are called F/S mode in this article. The protocol of high -speed mode is different from the F/S mode, called HS mode. DAC8574 supports 7 addresses; 10 -position address and general call address do not support.

F/S mode protocol

The host starts the data transmission by generating start -up conditions. The starting condition is that when the SCL is a high to low on the SDA line, it is shown in Figure 47. All compatible devices should identify the startup conditions.

The host subsequently generates SCL pulse, and transmits 7 digits and read/write direction bits R/W on the SDA line. In all transmission processes, the host ensures that the data is effective. Valid data conditions require the SDA line to maintain stability during the entire high cycle of the clock pulse (see Figure 48). All devices can identify the address sent by the host and compare it with the internal fixed address. Only the device with a matching address can generate responses by pulling the SDA cable through the entire high cycle of the ninth SCL cycle (see Figure 49). When the confirmation is detected, the host knows that the communication link with the machine has been established.

The main device generates more SCL cycles to transmit data to the device (R/W bit 1) or from the device to receive data (R/W bit 0). In any case, the receiver needs to confirm the data sent by the sender. Therefore, the confirmation signal can be generated by the host or from the machine, which depends on which receiver. Nine -bit valid data sequences composed of 8 -bit data and 1 -bit confirmation can continue as needed.

In order to send a signal of the end of the data transmission, when the SCL cable is at a high level, the host generates the stop condition by pulling the SDA cable from low to high (see Figure 47). This will release the bus and stop the communication link with the address. All compatible devices must identify stop conditions. When receiving stop conditions, all devices know that the bus is released, they are waiting for a startup condition, and then a matching address.

H/S mode protocol

When the bus is idle, the SDA and SCL lines are pulled up by the pull -up device.

The host generates a startup condition, and then follows an effective serial byte containing the H/S main code 00001xxx. This transmission is performed at a speed of no more than 400 kbps in the F/S mode. No device is allowed to confirm the H/S main code, but all devices must identify it and switch it to support 3.4 Mbps fuckdo.

then, the host generates repeated startup conditions (the repeated start -up conditions are the same time as the startup condition). Under this repeated start -up condition, the protocol is the same as the F/S mode, but the transmission speed is as high as 3.4 Mbps. Stop the condition to end the H/S mode and switch all the internal settings from the device to support the F/S mode. Stop conditions should be used, and repeated startup conditions should be used to ensure that the bus is in H/S mode.

DAC8574 I2C update sequence

DAC8574 requires a startup condition, an effective I2C address, a control bytes of control bytes , An MSB byte and an LSB byte update. After receiving each byte, the DAC8574 is confirmed by pulling the SDA cable within a high cycle of a single clock pulse. Effective I2C address Select DAC8574. Control the operating mode of the selected DAC8574 selected by byte settings. Once the byte is controlled, the operating mode is selected, and the DAC8574 expects an MSB byte to follow an LSB byte in order to update the data. DAC8574 The decline of the confirmation signal after the LSB byte is updated.

Before the operation mode is needed, there is no need to send the control bytes. Control the byte position to continuously determine the update type. Therefore, for the first update, DAC8574 requires a startup condition, an effective I2C address, a control byte, a MSB byte, and an LSB byte. For all continuous updates, as long as the control command remains unchanged, DAC8574 requires a MSB byte and a LSB byte.

Use I2C high -speed mode (FSCL 3.4 MHz), and the clock runs 3.4 MHz. Except for the first 16 -bit DAC update except for the first update, Confirm the signal, LSB byte, confirmation signal), the speed is 188.88 KSPS. Use fast mode (FSCL 400 kHz), the clock runs at 400 kHz, and the maximum DAC update rate is limited to 22.22 KSPS. Once the stop condition is received, the DAC8574 will release the I2C bus and wait for the new startup conditions.

The address byte is the first byte received from the main device after starting the condition. The top five (MSB) of the address is 10011 when they leave the factory. The two digits of the address are device selection sites A1 and A0. A1, A0 address input can be connected to VDD or digital GND, or can be actively driven by TTL/CMOS logic level. During the power sequence of DAC8574, the device address is set by the status of these pins. As many as 16 devices (DAC8574) can still be connectedTo the same I2C bus.

DAC8574 also supports broadcast addressing. Broadcast addressing can be used to simultaneously update or close multiple DAC8574 devices. The DAC8574 aims to work with other members of the DAC857X and DAC757X series to support multi -channel updates. Use the broadcast address, regardless of the status of the address pin, DAC8574 will respond. Support broadcasting only in the writing mode (the host is written in DAC8574).

The highest effective byte

Most valid byte MSB [7: 0] from 16 -bit binary D/A Convert the 8 maximum effective bit of data. C0 1, MSB [7], MSB [6] indicates the power -off operation, as shown in Table 8.

The minimum effective byte

The minimum effective byte LSB [7: 0] is composed of 8 minimum valid bites of the 8 -digit binary D/A conversion data. DAC8574 The decline of the confirmation signal after the LSB [0] bit is updated.

Default recovery condition

If the user starts the specified channel back without writing the data to the specified channel first, then the default recovery is zero, because the return register is referred to the register, because the return register is the register. Initialized in the power -on reset stage to 0. LDAC function

According to the control bytes, the decrease of DAC's confirmation signal after the LS byte is updated simultaneously. Only when external timing signals are used to update all channels for DAC asynchronous, LDAC pin is needed. LDAC is a positive edge trigger asynchronous input, allowing four DAC output voltage to update with temporary register data at the same time. LDAC trigger can only be used after the buffer temporary register is correctly updated by the software.

DAC8574 register

DAC8574 as a machine receiver-standard and fast mode

FIG. 51 shows the standard and fast mode main mode. The transmitter, address DAC8574 from the 7 -bit address.

DAC8574 as a subordinate receiver-high-speed mode

FIG site.

Under the standard/fast mode, the main transmitter writes from the receiver (DAC8574)

All writing access sequences are device address (R/R/R/ W 0) Start, then control bytes. This control byte specifies the operation mode of the DAC8574 and determines which channel to access the DAC8574 in the subsequent reading/writing operation. Control byte (PD0) LSB determines whether the following data is power -off or conventional data.

In the case of (pd0-bit 0), DAC8574 expects to receive data in the following order: high byte-low byte-high byte-low byte ... until the stop of I2C bus stops Conditions or repeated start -up conditions (refer to the data input mode part of Table 4).

In (pd0 -bit 1), DAC8574 expects to receive 2 -byte of power -off data (see the power -off mode part of Table 4).

(1), using repeated startups to ensure the safety of the bus operation, and circulate the post -addressing stage in order to write it next time.

(2), once the DAC8574 address and send control bytes correctly, high byte-low byte sequence can be repeated until the stop conditions or repeated startup conditions are received.

In HS mode, the main transmitter is written from the receiver (DAC8574)

When the data is written to DAC8574 in HS mode, the host began to transmit the so -called HS in F/S mode in F/S mode. Main code (0000 1xxx). The main device does not allow HS to confirm, so the host code is not allowed.

Then, the host switches to the HS mode and emits a repeated start -up condition, followed by the address byte (R/W 0), and then the DAC8574 is confirmed by lowering the SDA. This address bytes are usually followed by the control bytes, and it is also confirmed by DAC8574. The LSB of the control byte (PD0) determines whether the following data is power -off or conventional data.

In the case of (pd0-bit 0), DAC8574 expects to receive data in the following order: high byte-low byte-high byte-low byte ..., until I2C bus is recognized Stop conditions or repeat the starting conditions (see Table 5 HS mode writing order-data).

In the case of (pd0-bit 1), DAC8574 is expected to receive 2 bytes of power-off data (refer to Table 5 HS mode to sequence-power off).

(1), using repeated startups to ensure the safety of the bus operation, and circulate the post -addressing stage in order to write it next time.

(2), once the DAC8574 address and send control bytes correctly, the high byte and low byte sequence can be repeated until the stop or repeated startup conditions are received.

DAC8574 as a slave transmitter-standard and fast mode

FIG. 53 shows the standard and fast mode main transmitter. The main transmitter uses a 7-bit address address to DAC8574 to the transmitter.

DAC8574 as a passing machine-high-speed mode

Figure 54 shows the DAC8574 (7 -bit address) of the I2C host address in a high -speed mode as a transmitter from the machine.

Standard/Fast mode, the reader of the main receiver (DAC8574) in the fast mode

When reading the data from DAC8574, the user uses a address word from a address word. At the beginning of the festival (R/W 0), the DAC8574 will be confirmed by lowering the SDA. This address bytes are usually controlled by bytes, and DAC8574 will also confirm it. After that, the host has a repeated start -up condition, and the address is re -sent (R/W 1). This was confirmed by DAC8574, indicating that it is ready to send data. Then, according to (PD0), read two or three bytes from DAC8574. The values u200bu200bof BUFF-SEL1 and BUFF-SEL0 determine which channel data is read back. Subsequent stop conditions.

Under (PD0 bit 0), DAC8574 transmits 2 bytes of data, and high bytes are subsequently low (reference Table 2). Data Reading Mode-2 bytes).

In (pd0 -bit 1), DAC8574 transmits 3 bytes of data, power -off bytes, high bytes, and low bytes (see Table 2). Data Reading Mode-3 bytes).

The main receiver reads the data from the launch machine (DAC8574) in HS mode

When reading the data to DAC8574 under HS mode, the host begins Transfer, the HS main code (0000 1xxx) in the F/S mode. Any device is not allowed to confirm the HS main code, so the HS host code follows a not acKnowledge behind.

Then, the host switches to the HS mode and emits a repeated start -up condition, followed by the address byte (R/W 0), and then the DAC8574 is confirmed by lowering the SDA. This address bytes are usually controlled by bytes, and DAC8574 will also confirm it.

Then, there is a repetitive startup condition started by the host, which is submitted by (R/W 1). This is confirmed by DAC8574, indicating that it is ready to transmit data. Then read two or three bytes of data from DAC8574 according to (PD0). The values u200bu200bof BUFF-SEL1 and BUFF-SEL0 determine which channel data is read back. Subsequent stop conditions.

Under (PD0 digits 0), DAC8574 transmits 2 bytes of data, first high byte, and then low byte (refer to the sequence of reading 7 HS mode).

In (PD0 -bit 1), DAC8574 transmits 3 byte data, high bytes after power -off bytes, and then low bytes (refer to the sequence of reading 7 hs mode).

Putting -up reset

DAC8574 includes the power -on reset circuit and control the output voltage during the power -power period. When power is powered, the DAC register is full and the output voltage is 0 V. Before the DAC is effectively written into the sequence, it keeps there. This is very useful in the application. In these applications, when DAC is in the process of power, it is very important to understand the output status of DAC. Before power -on, the device's pin must not be tuned.

Power off mode

DAC8574 contains four independent power -off operation modes. These modes can be programmed by the two highest effective bits of the MSB byte, while (Ctrl [0] pd0 1). Table 8 shows how the status of these bits corresponds to the operation mode of the device.

When (ctrl [0] pd0 0), the device works normally. At 5V per channel, its normal power consumption is 250 μA. However, for the three kinds of power -off mode, the power current was reduced to 200NA at 5V (50NA at 3V). Not only did the power current decrease, but the output level also switched from the output of the amplifier to the well -known resistance network. This has an advantage, that is, in the power -off mode, the output impedance of the device is known. There are three different options: the output is connected to GND or left (high impedance) inside 1 k resistor, 100 k The output level is shown in Figure 55.

When the power shutdown mode is activated, all linear circuits will be closed. However, the content of the DAC register is not affected during power off. For VDD 5 V, the time to exit power is usually 2.5 μs; for VDD 3 V, the time to exit power is usually 5μs. (For more information, see the typical curve part.)

DAC8574 provides a flexible power off -power interface based on channel register operation. The channel is composed of 16 -bit DAC, a temporary storage register (TR), and a DAC register (DR) with a power -off circuit. TR and DR are 18 -bit. Two MSB represents the power -off condition, and 16 LSB represents the data of TR and DR. By using the 17th and 18th bits of TR and DR, the power -off condition can be temporarily stored and used as data. Internal circuits ensure that when setting the power loss logo (CTRL [0] PD0), MSB [7] and MSB [6] are transmitted to TR [17] and TR [16] (DR [17] and DR [16])))))) Essence Therefore, DAC8574 regards the power -off conditions as data, and all operating modes are still valid for power -off. You can broadcast the power condition to all DAC8574 in the system, or turn off the channel at the same time as updating the data on other channels.

current consumption

DAC8574 usually consumes 225 μA at VDD 5V, and 200 μA is consumed when VDD 3V, including reference current consumption. If you add VIH LT; LT; VDD, the digital input terminal may occur. For the most effective power operation, it is recommended to use the CMOS logic level at DAC's digital input terminal. In the power -off mode, the typical current consumption is 200 mAh. The delay time of 10 to 20ms after sending a power off command to DAC is usually sufficient to reduce the power -off current to less than 10 μA.

Drive resistance and capacitor load

DAC8574 output level can drive up to 1000 PF load while maintaining stability. In the range of offset and gain error, when the capacitance load is driven, the DAC8574 can run rails. 2 K resistance load can be driven by DAC8574, and at the same time, it can be adjusted very well. When the output voltage is close to each orbit, the load adjustment error increases. When the output of the DAC is driven to the right track under the resistance load, the PMOS transistor in each AB output stage can enter the linear area. When this happens, the increased infrared voltage drop will deteriorate the linear performance of DAC. This will only occur within the front 20 millivoltage range of the DAC digital input to the voltage output transmission characteristics. If a good linearity is required at a full range (under the resistance load conditions), the reference voltage appropriately applied on the DAC8574 can be reduced to the power supply voltage for the VDD to eliminate this situation.

String and AC performance

DAC8574 architecture is a separate resistance strings for each DAC channel to achieve ultra -low stringing performance. During the adjustment of the adjacent channel, the DC disturbances seen on a channel are usually less than 0.5 LSBS. The measured interchanging skewers (for the full scale, the 1KHz sine wave output generated on a channel, measured on the remaining output channel) is usually lower than -100DB. In addition, the DAC8574 can achieve the typical communication performance of the 96 DB signal -to -noise ratio (SNR) and 65 DB total harmonic distortion (THD), making DAC8574 a reliable choice to require high signal -to -noise ratios at 4 kHz or below.

Output voltage stability

DAC8574 has good temperature stability within the prescribed temperature range of the device, and the typical output voltage drift is ± 3 ppm/° C. This allows the output voltage of each channel to remain within the range of ± 25 μV within the range of the environmental temperature change range of ± 1 ° C. The performance of good power suppression ratio (PSRR) performance reduces the power noise on the VDD from the output end to less than 10 μV-S. Combining good DC noise performance and real 16 -bit differential lineivity, DAC8574 has become an ideal choice for closed -loop control applications.

Stable time and output failurePerformance

For the full scale code of the input, the stable time within 16 -bit accurate range of DAC8574 can be implemented within 10 μs. In the worst case, the adjustment time between continuous code changes is usually less than 2 μs. DAC8574's high -speed serial interface design supports up to 188KSPS update rates. For full marking output swing, when the 200 PF capacitance load is driven, the output level of each DAC8574 channel usually shows over -rushing and downward rushing less than 100 MV. Because the conversion of code to code does not span the boundary of the NX4096 code, the change from code to code is very low (~ 10 μV). Due to the internal section of the DAC8574, each intersection of the NX4096 code will appear small -fault boundary between code to code. When n 15, the fault may be close to 100mvs, but it is resolved within ~ 2 μs.

申请信息

以下各节给出了在各种应用中使用DAC8574的电路示例和提示

基本连接

对于许多应用， It is very simple to connect DAC8574. The basic connection figure of DAC8574 is shown in Figure 56. 0.1 μF bypass power container helps to provide an additional current required for the power supply.

DAC8574 direct with standard mode, fast mode and high -speed mode i2C controller interface. Any micro -controller's I2C peripheral device, including the main device and non -multiple main I2C peripheral devices, work with DAC8574. DAC8574 does not execute the clock stretch (that is, it never pulls the clock line). Therefore, unless other devices are on the same I2C bus, it is not necessary to provide it.

Both the SDA and SCL lines need to be pulled, because the I2C bus drive is leaked. The size of these resistors depends on the working speed of the bus and the capacitance on the bus. The higher the resistance value, the smaller the power consumption, but it will increase the conversion time on the bus, thereby limiting the speed of the bus. Low -value resistors are at the cost of higher power consumption, allowing higher speeds. The long mother line has higher capacitors and requires smaller pull -up resistance to compensate. If the pull -up resistance is too small, the bus drive may not be pulled down.

Most micro -controllers have a programmable input/output pin for most micro -controllers that use the GPIO port

These pins can be set to input or output in the software. If the I2C controller is not available, the DAC8574 can be connected to the GPIO pin, and the I2C bus protocol is simulated in the software, or the bit collision. Figure 57 shows an example of a single DAC8574.

By setting the GPIO line to zero, and switching between the input and output mode to apply the proper bus state, it can achieve G G's G GP, which can achieve G G's G G, Grear can achieve G G's G G.Pioch pins collide. In order to drive the low line, the pins are set to the output zero; in order to make the line go, the pins are set to input. When PIN is set to input, you can read the state of the PIN; if another device pulls the line down, the value in the input register of the port will be zero.

Please note that there is no upper pull resistor on the SCL line. In this simple case, there is no need for a resistor. The microcontroller can simply keep the line output and set it to 1 or 0 as needed. It can do this because DAC8574 never reduces the clock line. This technology can also be used for multiple devices, and because there is no resistance to rise, it has the advantages of lower current consumption.

If any device on the bus may reduce its clock line, the above method will not be applied to the SCL line should be high Z or zero, and a pull -up resistor is provided according to routine. It should also be noted that this cannot be implemented on the SDA line under any circumstances, because the DAC8574 will drive the SDA line from time to time like all I2C devices.

The GPIO port of some microcontrollers built up the optional strong pull circuit. In some cases, they can be opened and used to replace the external pull -up resistors. Some microcontrollers also provide weakly pulling up, but it is usually too weak for i2C communication. Test any circuit before investing in production.

Using REF02 as a power supply for DAC8574

Since DAC8574 requires a very low power current, a possible configuration is to use the REF02+5V precision reference voltage to provide DAC8574 power supply input and reference input input input and input input The required voltage, as shown in Figure 58. If the power supply is very noisy or the value of the system's power supply voltage is not 5 V, this is particularly useful. The REF02 is the DAC8574 output stable power supply voltage.

If you use REF02, the current provided to DAC8574 is 950 μA (typical value), and the maximum value when VDD 5 V is 1600 μA. When loading the DAC output, the REF02 also needs to provide a current to the load. The total typical current (5 k load on a single DAC output) is: 950 μA + (5 v / 5 k ) 1.950 ma

The load adjustment of Ref02 is usually 0.005 %/ma, the error of the 1.950-MA current generated is 488 μV. This corresponds to the 6.4 LSB error in the output range of 0 V to 5 V.

Ref3040 can also be used to generate 4.096 volt voltage from 5 volts of power.

Output of ± 5 V, ± 10 V and ± 12 V for precision industrial control

Industrial controlApplications require multiple feedback circuits composed of sensors, ADC, MCUs, DACs and actuators. The accuracy and circuit speed of the loop are two important parameters of such control circuits.

Circle accuracy:

In the control loop, the mold converter must be accurate. The linear error error of the displacement, gain and DAC is the factor that determines the accuracy of the ring. As long as there is a voltage in the transmission curve of the monotonous digital modulus, it can be found an