AD9235BRUZ

Product Details

The AD9234 is a dual, 12-bit, 1 GSPS analog-to-digital converter (ADC). The device contains on-chip buffers and sample-and-hold circuits and is designed for low power consumption, small size, and ease of use. This product is used to sample wide bandwidth analog signals. The AD9234 is optimized for wide input bandwidth, high sampling rate, excellent linearity, and low power consumption in a small package.

This dual-channel ADC core features a multi-stage, differential pipeline architecture with integrated output error correction logic. Each ADC has a wide bandwidth buffered input that supports a variety of user-selectable input ranges. An integrated voltage reference simplifies design. The data output of each ADC is internally connected to a selectable divide-by-2 clock.

The AD9234 has built-in features that simplify the automatic gain control (AGC) function in communications receivers. Using the ADC's fast detect output bits, a programmable threshold detector can monitor the input signal power. If the input signal level exceeds a programmable threshold, the fast detect indicator goes high. Due to the extremely short delay of this threshold indicator, the user can quickly turn down the system gain to avoid overrange at the ADC input. In addition to the fast detection output, the AD9234 also has signal monitoring capabilities. The signal monitoring module provides additional information on the signal being digitized by the ADC.

Users can configure the high-speed serial output of JESD204B subclass 1 in single, dual or quad configurations, depending on the acceptable channel rate of the receiving logic and the sampling rate of the ADC. Multi-device synchronization support is provided through the SYSREF± and SYNCINB± input pins.

The AD9234 has flexible power-down options to significantly reduce power consumption when needed. These features are programmable via 1.8 V to 3.3 V 3-wire SPI.

The AD9234 is available in a 64-lead lead-free LFCSP package and is specified over the industrial temperature range of ?40°C to +85°C. This product is protected by a US patent.

Applications

communication

Diversity multi-band, multi-mode digital receiver 3G/4G, TD-SCDMA, WCDMA, GSM, LTE

point-to-point radio system

Digital predistortion observation path

Universal Software Radio

Ultra Wideband Satellite Receiver

Instrumentation (spectrum analyzers, network analyzers, integrated RF test solutions)

digital oscilloscope

High-speed data acquisition system

DOCSIS 3.0 CMTS upstream receive path

HFC digital reverse path receiver

Features and Benefits

JESD204B (subclass 1) encoded serial digital output

Total power consumption per channel at 1 GSPS: 1.5 W (default setting

SFDR = 79 dBFS (340 MHz)

Signal-to-Noise Ratio (SNR): 63.4 dBFS (340 MHz, AIN = -1.0 dBFS

ENOB = 10.4 bits (10 MHz)

DNL = ±0.16 LSB

INL = ±0.35 LSB

Noise density = ~151 dBFS/Hz at 1 GSPS

DC Power: 1.25 V, 2.5 V and 3.3

No missing codes

ADC internal 1.0 V reference