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2022-09-16 16:00:09
BUF16820 with 14 -channel gamma voltage generator with programmable VCOM output and OTP memory
Features
14 channel gamma correction
2 VCOM output [123
]OTP memory on the film
10 -bit resolution
Rail -to -track output
Low power current: 1MA/CH
Power voltage: 8.5V to 18V
Digital power supply: 2.0V to 5.5V
Industry standard, dual -line interface: 3.4MHz high -speed speed speed ModeHigh ESD rated value: 4KV HBM, 1KV CDM, 200V mm
Software
Application
Replace resistor-based gamma solutions
TFT- LCD reference driver
Dynamic gamma control
Explanation buf16820
is a programmable benchmark voltage The generator is designed for gamma correction in the TFT-LCD panel. It provides 14 programmable outputs and two VCOM channels, and the resolution of each channel is 10 bits. It provides a one -time programmable (OTP) memory, allowing users to store gamar voltage on the chip. This does not require external EEPROM.This programmable replaced the traditional, time -consuming change of resistance to optimize the process of gamma voltage, and allows designers to quickly determine the correct gamma voltage of the panel. It can also be easily implemented without changing the hardware voltage. Each output is programmed through the two -line interface of industrial standards. Unlike the existing programmable buffer, the BUF16820 provides a high -speed mode that allows the clock speed to be as high as 3.4MHz.
For equipment with lower or higher channels, please contact your local sales or marketing representatives.
BUF16820 offers PowerPad #63722; software packages in HTSSOP-32. The specified temperature range is 40 ° C to+85 ° C.
BUF16820 Related Products
Typical features
TA +25 ° C, vs 18V, vsd 5V, VREFH 17vV , VREFL 1V, RL 1.5K ground, when CL 200pf, unless there is another instructions.
Application information
BUF16820 programmable reference volt In the channel, each channel has 10 -bit resolution. It allows a very simple and efficient adjustment of gamma benchmark voltage and VCOM voltage. BUF16820 is programmed through high -speed standard dual -line interface. The BUF16820 provides a dual register structure for each DAC channel to simplify the implementation of dynamic gamma control. This structure allows pre -load register data to quickly update all channels at the same time.
Cushioner 1 9 can swing within the 200mv range of the positive electrode power supply rail, and swing within the range of 0.6V of the negative electrode power supply track. The positive buffer within the range of the negative rail 10.0 is powered by the rail 10.0 volt.BUF16820 can use 8.5V to 18V analog power supply voltage and 2V to 5.5V digital power supply. Digital power supply must be used or at the same time before or at the same time to avoid excessive current and power consumption; if you only connect to the simulation power supply for a long time, the device may be damaged. Figure 7 shows the regular requirements of power supply.
FIG. 8 shows the BUF16820 in the typical configuration. In this configuration, the BUF16820 device address is 74h. Once the data is received in the corresponding register (LD 0), the output of each digital modular converter (DAC) is updated immediately. For the maximum dynamic range, set VREFH vs 0.2V, VREFL GND+0.2V.
Overview of the dual -line bus
BUF16820 communicates through industrial standard dual -line interfaces to receive data from the mode. This standard uses the two -line open -road leakage interface to support multiple devices on a single bus. The bus is only driven to low logic. The device that initiated communication is called the main device. The device controlled by the main device is the host of the slaves to generate a serial clock on the clock signal line (SCL), the control bus access, and generate the start and stop condition.In order to address specific devices, when the SCL is at high electricity, the host is used to sign the data signal line (SDA) from high logicLow -to -low logic levels start the startup condition. All the machines on the bus are shifted from the address byte by bytes, and the last one said whether it is necessary to read the operation or write operations. During the ninth clock pulse, the sub -addressing machine responded to the host by generating a response and lowering the SDA.
Then start the data transmission, send 8 -bit data, and then send a confirmation bit. During the data transmission process, when the SCL is high, the SDA must be stable. When SCL is high, any change of SDA will be explained as startup or stop conditions.
Once all data is transmitted, the main device will generate a stop condition. When SCL is high, SDA is pulled from low to high.
BUF16820 can only be used as a device; therefore, it never drives SCL. The SCL pin is only the input of BUF16820. Table 1 and 2 summarize the address and command code of the BUF16820, respectively.
Processing BUF16820
The address of the buf16820 is 111010x, where X is the state of the A0 pin. When the A0 pin is low, the device will be confirmed on the address 74h (1110100). If the A0 pin is high, the device will be confirmed on the address 75h (1110101).
Other valid addresses can be implemented by simple mask changes. Please contact your TI representative to obtain information.
Data rate
The dual -line bus runs with one of the three speed modes:
*Standard -allow clock frequency to reach 100kHz ;*Quick -The allowable clock frequency is as high as 400kHz;
*High -speed -The allowable clock frequency is as high as 3.4MHz.
BUF16820 is completely compatible with all three modes. Under standards or fast mode, the use of equipment does not require special operations, but the high -speed (HS) mode must be activated. To activate the HS mode, send a special address byte 00001xxx after the start -up condition, SCL 400kHz; the XXX is the only bit of the host of HS, which can be any value. This byte is called HS main code. (Please note that this is different from the normal address bytes, the low position does not indicate the status of reading/writing.) No matter what the last three digits are, the BUF16820 will respond to the HS command. The BUF16820 will not confirm this byte; the communication protocol prohibits the confirmation of the HS main code. After receiving the main code, the BUF16820 will open its HS mode filter and communicate at a frequency of up to 3.4MHz. By generating uninterrupted repetitions, you can start additional high -speed transmission without sending HS mode bytes. BUF16820 will exit the HS mode under the next stop condition.
General call reset and power power
BUF16820 response general call reset, that is, the address byte 00h (0000000000), and then the data byte 06H (0000 0110). BUF16820 admits these two bytes. After receiving the general call reset, the BUF16820 will execute completely internal resetting, as if it has been disconnected and then turned on. It always confirms the general call address bytes of 00H (0000 0000), but it is not confirmed that any general call data bytes other than 06H (0000 0110) are not confirmed.
BUF16820 automatically executes reset after power generation. As part of the reset, the BUF16820 is configured to all outputs, which is changed to a programming OTP memory value, or it is changed to 0000 without programming the OTP value.
When sending the device address, the BUF16820 resets all outputs to OTP memory values u200bu200b(if the OTP value is not programmed, then reset to 0000), and then send an effective DAC address, D7 to D5 -bit settings to the D5 bits to ""100"". If these bits are set to #39; 010 #39;, only the DACs addressing the maximum effective bytes and the lowest effective bytes below will be reset.
Output voltage
The output value of the buffer is determined by the decimal value of the binary input code for the binary input code for the buffer. Use equation (1) Calculate this value:
The effective voltage range of the reference voltage is:
buf16820 output can be available. Implement a full volume voltage output change in a typical 5μs without the need for intermediate steps.
Output locks
The update DAC register is different from the update DAC output voltage, because the BUF16820 has a dual cushioning register structure. There are three ways to lock the transmitted data from the storage register to the DAC to update the DAC output voltage.Method 1: You need to set the 闩 闩 引 (LD) LOW, LD LOW. Whenever the corresponding register is updated, it updates each DAC output voltage.
Method 2: LD HIGH is set on the outside to allow all DAC output voltage to maintain its value during the data transmission period, until LD LOW, and then update the output voltage of all DACs to a new register value. Use this method to transmit future data sets in advance to prepare very fast output voltage updates.
Method 3: Software control. LD remains a high level. When the main device is written ""1"" in the 15th place of any DAC register and the 14th bits are written ""0"