Function description

LMX2306/16/26 is a single -piece integrated 2.3V to 5.5V operation with a premature frequency synthetic Silicon BICMOS 0.5 μl. LMX2306 contains 8/9 dual-mode pre-scoring device. MA.

Application

LMX2306/16/26 has ultra -low current characteristics

Ultra -low current consumption design for generating very stable low current

2.5V VCC JEDEC standard compatible noise signal, used to control

program available or logical power failure mode: radio frequency transceiver.

—ICC u003d 1 μA, typical value is 3V

] Dual -mode pre -scoring device:

and LMX2316 and LMX2326 have a 32/33

- LMX2306: 8/9 dual -mode pre -division. ]

—LMX2316/26: 32/33 A Digital Locking Ring Ring Technology. When?

Optional charge pump trio mode, combined with high -quality reference oscillator and ring circuit filter, LMX2306// 16/26 Provide feedback

The selected fast lock mode, which has a timeout regulating voltage for voltage control oscillator, in order to reflect the signal of a low phase noise noise.

Microwire interface string The line data passes

Digital lock detection three-line interface (data, enable, clock).

Power consumption: LMX2306-3V is 1.7 ma, LMX2316-

LMX2306 LMX2306 /16/26 synthesizer can be provided in a Wi Wireless LAN (WLANS) 16 -pin Tssop surface installation plastic packaging.

Cable TV Tuner (CATV)

Pagoda

Other wireless communication systems

Electric characteristics

VCC u003d 3.0V, VP u003d 3.0V; 40 ° C LT; TA LT; 85 ° C, unless there are other regulations

(1) except except Win and Austin.

(2) ICPO description see Table 1

The absorption current of the charge pump under i1 u003d VCPO u003d vp ΔV

The charge pump absorbing current under i2 u003d vcpo u003d vp/2

The charge pump under i3 u003d vcpo The charge pump Absorption current u003d ΔV

The charge pump source current under i4 u003d vcpo u003d vp ΔV

The charge pump source current under i5 u003d vcpo u003d vp/2

The charge pump source under i6 u003d VCPO u003d ΔVΔV u003d positive and negative voltage offset. Depending on the VCO tuning range and

, the VCO is grounded. Typical values u200bu200bare between 0.5V and 1.0V.

The simplified box diagram below shows 21 -bit data register, 14 -bit R counter, 18 -bit N counter, and 18 -bit function 闩 lock locks. (The middle lock is not displayed). The data stream is moved (in Le) to enter data, MSB is preferred. The last two are the control level. The data is transmitted to the counter as follows:

The programmable benchmark frequency division

If the control bit is [C1, C2] u003d [0,0], The data is transmitted from the 21-bit displacement register to the-bit R counter in the locks of the setting 14. 4 -bit R15 – R18 is used for test mode, and should be set to 0 when normal use. LD precision bit R19 is described in the lock detection output characteristic section. The serial data format is shown below

(1) to R14: These bits select the frequency ratio of programmable reference frequency division.

(2) The division ratio is less than 3.

(3) Diversion ratio: 3: 16383

The programmable division (n counter)

n counter is by 5 swallow counter (A counter) and 13 digits and 13 digits Programmable counter (B) composition counter). If the control bit is [C1, C2] u003d [1,0], the data is transmitted from 21 displacement registers to 5 -bit locks (setting a swallow (A) counter), 13 -bit locks (set 13 -bit programming can be programmable (B) counter), and the GO bit (see the FastLock mode part) MSB is preferred. For LMX2306, the maximum N value is 65535, and the minimum N value is 56. For LMX2316/26, the maximum N value is 262143, and the minimum N value is 992. The serial data format is shown below.

pulse swallowing function

fvco u003d [(p x b)+a] x fosc/r

fvco: external pressure control: external pressure control Oscillator (VCO)The output frequency

B: The preset frequency frequency of the 13 -bit programmable counter (3 to 8191) of the binary 13 -bit programmable counter

A: The preset frequency frequency of the 5 -bit swallow counter of the binary (0≤a≤31; A≤b, for LMX2316/26) or (0≤a≤7, A≤blmx2306)

FOSC: The output frequency of the external reference frequency oscillator

R: Binary 14 -bit programmable reference counter (3 to 16383) preset frequency frequency frequency

P: LMX2306 dual -mode pre -division pre -scorer's preset modulus; P u003d 8 of LMX2316/26; P u003d 32

Function and initialization Lock

The function locks and initialization locks are written into the same register. (See the later device programming first applied to the VCC part for initialized lock description.)

function description

f1. Allow N and R counters to reset. After power -on, the F1 digits need to be disabled, and then the N counter recovery the count R counter in a ""Close"" alignment method. (The maximum error is a pre -scoring cycle).

Please refer to the power -off operation section.

3-5. Control the output of folding sales. See the folding really worth. See Table 4.

Sixth. Phase detector polarity. According to the characteristics of the VCO, F6 bits should be set accordingly. The VCO characteristic is that the F6 should be set as high; when the VCO feature is negative, the F6 should be set to high and low

Use bit F7 to set the charge pump three -state. For normal operations, the bit is set to zero.

When the FastLock enabled bit is set, the components will be forced into one of the four FastLock mode. See the instructions in Table 5, FastLock decodes.

Fastlock control bit determines the operation mode when it is in FastLock (F8 u003d 1). In the fast lock mode, FLO can be used as a general output, which is controlled by that bit. For F9 u003d 1, FLO is very high and for F9 u003d 0, FLO is very low. See Table 5 in the truth.

10. The timeout of the timeout counter is set to 1 to enable the timeout counter. See Table 5 in the truth.

11-14. Use bit F11-14 Set FastLock timeout counter. Table 6 Show counter value.

15-17. Functional Bit F15 – F17 is used for test mode. When normal use, it should be set to 0

18. Please refer to the power-off operation part.

19. Functional F19 is used for test mode and should be set to 0 when normal use.123]

Power off operation

When the CE pin is high, the bits F [2] and f [18] provide a programmable power off mode. When the CE is low, the parts are always disabled regardless of whether the power is disconnected. Reference Table 3. Both synchronization and asynchronous power off mode can be achieved by selecting micrine. When f [2] bit (power off) becomes high, if F [18] bit (power -off mode) is high, power failure occurs. If f [18] is low and f [2] is higher, asynchronous power breaks occur. In synchronous power -off mode (f [18] u003d high), the power -off function is selected from the charge pump to prevent unnecessary frequency jump. Once the [F] bit is loaded to the second part of the program, the F position will enter the power -off mode after the first continuous charge pump event. In the asynchronous power break mode (f [18] u003d low), the device immediately power off the data in the F position after the low -lock lock. [2]. The device will immediately return to the active power increase in the synchronization or asynchronous mode to lock the low data to the F bit [2]. In the synchronization or asynchronous mode, the living conditions are excited, including the CE pin activation

Power off has the following effects:

Remove all effective DC current paths.

Forced R, N, and timeout counter are in its loading state.

Three -state charge pump.

Reset the digital lock detection circuit.

Turn the FIN input to a high impedance state.

Disable the oscillator input buffer circuit.

Microwire controls the activation state and can load data.

Lock detection output characteristics

When the VCO frequency is in the ""lock"" state, the output provided. When the ring is locked and the leakage is opened, the detection mode is selected. The pins output high and the narrow pulse is low. When the digital lock detection is to select this option, when the absolute phase error of the three or five continuous phase is less than 15ns, the output will reference the high -frequency detector reference cycle, depending on the value of R [19]. Once the lock is detected, the output remains unchanged unless the absolute phase error of a single reference cycle exceeds 30 ns. Set the charge pump to TRI status or power off (P2, F18) will make the digital lock detection and reset the unlocking state. LD precision drill, when R [19], R [19] will choose five continuous reference loops instead of three to enter the lock state u003d high.

Lock detection filter calculation

can determine the opening condition of the filter after detecting the missing amount in the lock state. The locking conditions can be specified as a continuous specific quantity (N) benchmark cycle or duration (d), where the phase detector phase error is less than the reference value period. In an example of 10 kHz at the reference period of the phase detector, you can choose to go through 5 companiesThe lock threshold that occurs when comparison is compared, and the phase error is 1,000 times shorter than the reference cycle (100 ns). Here n u003d 5, f u003d 1000. For the lock detection filter shown in FIG. 3, when the output is detected with the lock with the Mingqu (only activity receiver) lock, the resistance value of the R2 should be selected as the coefficient of F*R1. Therefore, if the resistance R1 is pulled only at a low of 1/1000 of the reference cycle, its ""effective"" resistance will be the same as that of R2. The average resistor under the duty cycle of the two seems to be two resistors of 1000 × R1. They are connected to the power supply voltage and their public node voltage (VC) is VCC/2. The phase error is greater than the benchmark 1/1000 cycle cycle to drag the average voltage of the node VC below VCC/2, which indicates that the node is locked. If the constant of time R2*C1 is now calculated as N*reference cycle (500 μs), the node voltage VC will be lower than VCC/2 with an average pulse width of more than 100ns.

Quick lock mode

FastLock enables designers to realize fast frequency conversion and good phase noise performance dynamic dynamic changes in the lock ring bandwidth through the following methods. Quick lock mode allows the seamless transition of broadband lock ring to quickly lock to low phase noise narrow belt lock. Maintain consistent gain and phase margin by changing the charging pump current, counter value, and ring filter damping resistance. The four fast lock models in Table 5 are similar to the technology similar to the Texas Instrument Company LMX233X series. When the F8 is high, it is selected by F9, F10 and N19. Model 1 and 2 change the circuit bandwidth is twice the original, while the mode 3 and mode 4 change the four times the circuit bandwidth. Mode 1 and 2 increase the size of the charge pump 4 times, and should be used to obtain a consistent gain and phase margin with R2 #39; u003d R2. Mode 3 and mode 4 increase the size of the charge pump, and reduce the value of the counter by 4 times. R2 #39; u003d #8531; R2 is used in the consistent stability of the mode 3 and 4. When the F8 is low, the FastLock mode is disabled, the F9 controls the FLO output level (FLO u003d F9), and the N19 determines the charging pump current (N19 u003d low → icpo u003d 250μA, N19 u003d high → icpo u003d 1 ma) Essence

(1) When the GO bit n [19] is set to 1, the part is forced into the high -gain mode. When the timeout counter is activated, the terminal loop is reset to 0 to 0. If the timeout counter is not activated, N [19] must be re -programmed to zero in order to remove the state. For explanations of each individual fast lock mode, see below.

There are two ways to open and close FastLock. In programming the device in any FastLock mode, the GO bit n [19] must be set to

1. Only to start FastLock operation. In the first method, the timeout can be used to use the counter (FastLock 2 and 4) to maintain a fast lock mode reference loop (up to 63 times), and then automatically reset the GO bit. In the second (fast lock 1 and 3), if there is no timeout counter, the PLL will be kept in the FastLock mode until the user passes through the micrine series. Once the GO bits are set to zero by the timeout counter or micrine, the PLL will then return to normal operation. This transformation does not affect the charge on the load filter capacitor with the charge pump output synchronization. This creates an almost seamless transition and standard mode between FastLock. In this mode, Flo's output level is in a low state in this mode. Before receiving the command, the device maintains this state and reset the N [19] bit to zero. Programming N [19] to zero will restore the device to normal operation*, that is, ICPO u003d 1x and FLO back to Sanzhou. FastLock mode

2. The same as mode 1, but the device's switching from FastLock is a timeout counter. Before the timeout counter countdown, the device will remain in the appropriate number of the phase detector cycle in the FastLock. At this time, the PLL resumes normal operation*. Quick lock mode

3. This mode is similar to the mode 1, because the output level of FLO is low and ICPO is switched to the 4X state. In addition, in the transient, the gain increases by 16 times. In Mode 1, the device will maintain this state until the Microwire command is received, the N [19] bit is reset to zero, and the device will return to normal operation*. FastLock mode 4 is the same as mode 3, but the device's switch from FastLock is controlled by the control timeout. Before the timeout counter countdown, the device will remain in the appropriate number of the phase detector cycle in the FastLock. At this time, the PLL resumes normal operation*.

The device programming after the first VCC

Three microfilm programming methods can be used to change the tight phase pair of function locks, R counter locks, and N counters through R and N counters. The counter locking content is allowed to increase the lock time after the cold state is reduced to maximize the power.

Initialize the sequence method

Load the function locks with [C1, C2] u003d [1, 1], and then load the R counter immediately, then load the n counter loading, and efficiently programming microfils Essence Use [C1, C2] u003d [1, 1] Loading the function lock program is the same with [C1, C2] u003d [0, 1] as a load -load functional lock, and provide additional internal reset pulses described below. This program sequence ensures that when the data of the n -counter data is locked, the counter is in the loading point component and will start counting in a close phase alignment. Use f locking characters [C1, C2] u003d [1, 1] Locking microfilment to get the followingResult:

Loading function 闩 lock content.

Internal pulse resets R, N, and over time stunts to the load state, and the three -state charging pump. If the function locks are programmed for synchronous power failure; CE u003d height, f [2] u003d high, f [18] u003d high, this internal pulse hair breaks. Please refer to the synchronous power outage instructions in the power off -power operation part. Note that the band gap benchmark and the oscillator input buffer of the pre -splitter is not affected by the internal reset pulse. When the counting is restored, it is allowed to be close to the phase.

Locking the first N counter data after initialization will activate the same internal reset pulse. Continuous N counter data loading without initialization load will not trigger the internal reset pulse.

CE method

When the part is in a power -off state, the statement of the program lock, the R counter 闩 and the N counter lock allows the less power consumption as possible. When the microfilic content is programmed, when the part is activated, the content of the R and N counters will continue to count in a close alignment. Please note that after the transition from low to high, the band voltage of the pre -splitter may require 1 μs duration oscillator to input buffer bias to achieve a steady state. CE can be used to control the components through pins to check the channel activities. This Microwire does not need to be re -programmed every time and disabled parts, as long as it has enabled or disabled the application VCC at least once at least once.

counter resetting method

This microfilm programming method includes a function locking load [C1, C2] u003d [0,1] to enable the counter to work reset, F [1] Essence Then load R and N to the lock, and then load the final function lock, the locks will disable the counter to reset. This provides the same tight phase alignment as the initialization sequence method to directly control the internal reset. Please note that the counter resetting the counter at the loading point and pumping the three -state charging pump, but it will not trigger the synchronous power off. The counter resetting method requires a comparison of an additional function lock loading and initialization sequence method.

Equipment programming Programming LMX2306, LMX2316 and LMX2326, first determine the required operation. The data register is programmed by 21 digits of data to the R counter, N counter, or F door. The function description part shows the bit of the R counter, and the corresponding N counter information. FLO programming information gives the lock part in the function and initialization. A typical number of a GSM application instance is given. In this example, the radio frequency output is locked under 950 MHz (FVCO), and the channel interval is 200 kHz (F comparison). The reference input of the crystal oscillator is 10 MMCs (FOSC) and the pre -scoring device value (P) is 32. The example of the two methods will be displayed below. Which counter or F of the last two bits (control bit C1 and C2) of each bit stream willLO mode has been programmed.For example, in order to program the R counter, C1 and C2 will be 0,0.Two problems immediately deal with n, r, or F bits that provide the Fabi and fast lock mode information.