Features

Suitable for car applications

relative accuracy (inl): ± 0.35 lsb

ultra -low failure energy energy : 0.1 nv-s

Low-power operation: 2.7 V is 100 μA

Power: 2.7-5.5-v Single power supply

Power off: 2.7 V is 0.05 μA

12-bit linearity and monotonability

] Output of voltage in the rail

Settling time: 5μs (maximum)

SPI compatible serial interface, with Schmidt trigger input: Maximum 50 MHz

Chrysanthemum chain function asynchronous hardware is clear to zero scale

specified temperature range: --40 ° C to+105 ° C [ 123]

Small, 2-mm × 3-mm, 12-lead USON packaging

z-suffix provides improved layers

Application

]

Portable battery power supply instrument

Digital gain and offset adjustment

programmable voltage and current source

programmable attenuation device

Industrial process control

ADAS radar application

collision warning

[

123] blind spot detection

Instructions

DAC7551-Q1

The device is a single channel, voltage output digital mode converter (DAC), which has excellence. The linearity and monotonism, and the proprietary structure that minimize the faulty energy. Low power consumption DAC7551-Q1 device can be powered from a single 2.7 to 5.5 volt power. DAC7551-Q1 output amplifier can drive 2-k and 200 PF rails to be loaded on rails, with a stable time of 5 μs. The output range uses an external reference voltage settings. 3 -line serial interface works at a clock frequency of up to 50 MHH, and is compatible with SPI compatibility #8482;, QSPI #8482;, Microwire, and DSP interface standards. The device contains a power -to -power reset (POR) circuit to ensure that the DAC output power is as high as 0V, and keep it under the voltage until the device is effectively written into the loop. The device has a power -off function and can reduce the current consumption of the device to below 2 μA.

DAC7551-Q1 has a small volume and low power consumption, which is very suitable for portable applications for battery operations. The power consumption at 5V is usually 0.5mW, and 0.23MW at 3V. The power consumption is reduced to 1μW in the power -off mode.

DAC7551-Q1 device is encapsulated by 12 stitches, and the specified temperature is -40 ° C to+105 ° C. Compared with standard devices, the Z suffix can be reduced.

Equipment information

(1), please refer to the appointment appendix at the end of the data table.

Figure Figure

Typical features

TA 25 ° C, unless otherwise explained.

Detailed explanation Overview

DAC7551-Q1 device is a 12-bit resistance string digital mold converter (DAC). The input input of no buffer allows the positive voltage reference as low as 0.25 V, up to VDD. The amplifier feedback input has better DC accuracy at the load point. The device is controlled by 16 -bit three -line three -tier peripheral interface (SPI), up to 50 MI, and multiple devices of chrysanthemum chain can be selected. Asynchronous clearance and power -off function allows software control to control reset and low power consumption. An independent logical power input means that the device can be used with different logic series within a wide range of power voltage range.

Figure Figure

Feature description

digital mode converter DAC and an output buffer amplifier composition. Figure 26 shows the universal box diagram of the DAC architecture.

The input coding of the DAC7551-Q1 device is a non-symbolic binary, which gives the ideal output voltage, such as equal form 1.

where:

D is the decimal value of the binary code loaded to the DAC register, from 0 to 4095.

resistance string

FIG. 27 shows the resistance string part. This part is just a resistor, each resistance value is R. Digital code loaded to the DAC register determine which node on the stringOn the top, the voltage is divided into the output amplifier. By turning off a switch connected to the amplifier, the voltage is distributed. The output of DAC is monotonous because it is a string of resistors.

Output buffer jams

Output buffer can generate orbit voltage at the output end, providing 0 V to VDD output range. The amplifier can drive a 2kΩ load and reach 1000pf on the ground. Figure 8, Figure 9, and 10 show the exchange and source of the output amplifier. In the case of output vacancy, the conversion rate is 1.8V/μs, and the half -scale stability time is 3 μs.

DAC external reference input

DAC7551-Q1 device contains non-buffer VREFH and VREFL reference inputs. The VREFH reference voltage can be as low as 0.25V, as high as VDD, because there is no net empty and foot space limit for reference amplifiers.

It is recommended to use the buffer benchmark (for example, the REF3140 device). The input impedance is usually 100kΩ.

The amplifier detection input

DAC7551-Q1 device contains a amplifier feedback input pin VFB. For voltage output operations, VFB must be connected to VOUT external. For DC points, more accurate DC connections should be made. VFB pin is also applicable to various applications, including digital control current sources. The feedback input pin is connected to the DAC amplifier's negative input terminal through the 100-kΩ resistor. The enlarged negative input terminal is grounded inside the 100-kΩ resistor (see Figure 26). These connections form a non -mutual amplifier configuration with a gain 2. The total gain is maintained as 1, because the resistance string has a configuration with 2. The grounding resistance seen at the VFB needle is about 200 kΩ.

Powering and reset

When powering, remove all registers and update the DAC channel with a zero -standard voltage. Before writing valid data, DAC output maintains this state. This setting is particularly useful in applications that are very important to understand the DAC output status when the device is powered on. To avoid turning on the ESD protection device, VDD and IOVDD should be applied before any other pins (such as VREFH). VDD and IOVDD have nothing to do with power supply sequence. Therefore, IOVDD can be proposed before VDD, or in turn.

Power off

DAC7551-Q1 device has a flexible power-off function. In the state of power off, users can flexibly choose DAC output impedance. During the power-off operation, DAC can have 1kΩ, 100kΩ or Hi-Z output-to-ground impedance.

Asynchronous clearance

After the CLR pin decreased, the DAC7551-Q1 output was immediately set to zero-standard voltage asynchronous. CLR letterThe number is reset all internal registers, so its function is similar to the power -on reset. The DAC7551-Q1 device is updated at the first rising edge of the synchronous signal, which occurs after the CLR pin returns to the high level.

IOVDD and level converters

DAC7551-Q1 device can be used to use different logic series of large-scale power supply voltage. To enable this useful feature, the IOVDD pin must be connected to the logical power supply voltage of the system. All DAC7551-Q1 digital input and output pins are equipped with level conversion circuits. The level shift in the input pin ensures that the external logic high voltage is converted to internal logic high voltage without additional power consumption. Similarly, the level shifting of the SDO foot converts the internal logic high voltage (VDD) into an external logic high level (IOVDD). For single power operations, the IOVDD pin can be connected to the VDD pin.

Points and differential linearity

DAC7551-Q1 device uses precision film resistance to provide excellent linearity and monotonicity. The linear error is usually within ± 0.35 LSBS, and the differential linear error is usually in ± 0.08 LSBS.

Failure energy

DAC7551-Q1 device adopts a proper architecture to minimize the failure energy. The small failure of the code -to -code is so low that they are usually hidden in broadband noise and are not easily detected. This DAC7551-Q1 fault is usually lower than 0.1 NV-S. This low failure energy has increased by more than 10 times compared with industrial substitution.

Equipment function mode

DAC7551-Q1 device uses four operating modes. By setting up PD0 (DB13) and PD1 (DB14) in the control register, these modes can be accessed. Table 1 shows how to use data bit PD0 (DB13) and PD1 (DB14) to control the operation mode. The DAC7551-Q1 device regards the power-off situation as data; all operating modes are still valid for power off. You can broadcast electricity to all DAC75551-Q1 device in the system. It is also possible to close a channel and update the data on other channels. In addition, you can also write a DAC register or buffer of the DAC channel that is disconnected. When DAC is powered on, DAC contains this new value.

When the PD0 and PD1 bits are set to 0, the device works normally. The typical consumption of the 2.7 V is 100 μA. For the three types of power -off mode, the power supply is reduced to 0.05μA at 2.7 V. As shown in Table 1, there are three different power off options. VOUT pins can be connected to GND inside the 1-kΩ resistor or 100-kΩ resistor, or it can be opened (High-Z). In other words, DB14 and DB13 11 indicate that the selected channel has a power -off condition for high Z output impedance.DB14 and DB13 01 and 10 represent 1-kΩ and 100-kΩ output impedance conditions of output impedance.

Programming

serial interface

DAC7551-Q1 device control through multi-functional 3-line serial interface control. The interface works at a clock rate of up to 50 MHz and is , QSPI, Microwire, and DSP interfaces are compatible.

16 -bit words and input shift register

The width of the input shift register is 16 bits. Under the control of SCLK in the serial clock, DAC data is loaded into the device in the form of 16 -bit characters, as shown in Figure 1. The 16 -bit characters listed in Table 1 consist of 4 control bits and 12 -bit DAC data. The data format is a direct binary, all 0 corresponding 0-v output, and all 1 corresponding full-scale output (VREF-1 LSB). The data first loads MSB (bit 15), of which the first two (DB15 and DB14) are unimportant. Bit 13 and position 12 (DB13 and DB12) determine the normal mode operation or power off mode (see Table 1).

Synchronous input is a level trigger input, which is used as frame synchronous signals and chips. Data can only be transmitted to the device when the synchronous pipe foot is low. To start serial data transmission, the synchronous pins should be low, and the minimum synchronization to SCLK drops the setting time T4. After the synchronous pin becomes lower, the serial data is transferred to the device input shift register on the upper edge of the SCLK, which lasts for 16 clock pulses.

After the synchronous tube foot becomes lower, the SPI is enabled, and the data is continuously transferred to the shift register of each drop edge of the SCLK input. When the synchronous tube foot is raised, the last 16 bits stored in the shift register are locked to the DAC register and DAC is updated.

The operation of the chrysanthemum chain

The chrysanthemum chain operation acts on the update of the serial connection device of the upper edge of the rising edge.

As long as the synchronous pins are high level, the SDO pin is in a high impedance state. When synchronous pins are reduced, the output of the internal displacement register is connected to the SDO pin. As long as the synchronous pins are low, the SDO pin is delayed to copy the SDIN signal with 16 cycles. In order to support multiple devices in the chrysanthemum chain, SCLK and synchronization signals shared between all devices, and the SDO pin of a DAC7551-Q1 device should be bound to the SDIN pin of the next DAC7551-Q1 device. For N devices in this chrysanthemum chain, the 16N SCLK cycle is required to move the entire input data stream. After receiving the 16N SCLK decrease edge, after the decrease of synchronization signals, the data flow becomes complete, and the synchronous tube foot can be raised to update N devices at the same time. The maximum SCLK speed of SDO operation is 10 MHz.

In the chrysanthemum chain mode, it is recommended to use a weak drop -resistant resistor on the SDO output pins, which provides SDIN data for the next device in the chain. For independent operations, the maximum clock speed is 50 MHz. For chrysanthemum chain operation, the maximum clock speed is 10 MHz.

Application and implementation

Note

The information in the following application chapters is not part of the TI component specification, TI does not guarantee its accuracy or integrity. TI's customers are responsible for determining the applicability of the component. Customers should verify and test their design implementation to confirm the system function.

Application information

Birch formation

Since the DAC7551-Q1 device has excellent linearity and low failure, the device is very suitable for waveform generation (from DC to 10kHz) Essence DAC7551-Q1 large signal stability time is 5 μs, supporting the update rate of 200KSPS. However, if the waveform to be generated is composed of a small voltage level between continuous DAC updates, the update rate can exceed 1msps. In order to obtain a high dynamic range, it is recommended to use the REF3140 device (4.096V) or the REF02 device (5V) to generate reference voltage.

Output of ± 5-v, ± 10-v, and ± 12-v was generated for precision industrial control

Industrial control applications require multiple feedback circuits, including sensors and mold converters (ADC), microcontroller (MCU), DAC and actuator. The accuracy and circuit speed of the loop are two important parameters of such control circuits.

Circle accuracy

DAC offset, gain and integral linear errors are also factor that determines the ring accuracy. As long as there is a voltage in the transmission curve of the monotonic digital converter, the voltage can be found and adjusted. On the other hand, DAC resolution and micro -linearity do determine the accuracy of the loop, because each DAC step determines the minimum incremental change that can be produced in the loop. The DNL error is less than –1 LSB (non -monotonicity) that causes the ring to be unstable. DNL error is greater than 1 LSB means unnecessary large voltage level jump and missed voltage targets. When the DNL error is large, the circuit will lose stability, resolution and accuracy. The DAC755X device has a typical DNL error of 12-bit guarantee and a typical DNL error of ± 0.08-LSB, which is the best choice for precision control circuits.

Ring speed

Many factors determine the speed of the control loop, such as ADC conversion time, MCU speed, and DAC setting time. Generally, the ADC conversion time and the MCU calculation time are the two main factors of controlling the ring time constant. Because the ADC conversion time usually exceeds the DAC conversion time, the stability time of DAC is rare is the main factor. DAC offset, gain, and linear errors can only slow down the ring speed during the startup processSpend. When the loop reaches a steady -state operation, these errors will not further affect the ring speed. According to the ringing characteristics of the loop transmission function, the DAC failure will also slow down the ring speed. DAC7551-Q1 has the maximum data update rate of 1-MSPS (small signal), which can support high-speed control circuits. The ultra-low fault energy of the DAC7551-Q1 device significantly improves the stability of the loop and the stability of the ring circuit.

Typical application

generated industrial voltage range

For the control loop application, DAC gain and offset error are also important parameters. This consideration can be used to reduce the fine -tuning and calibration costs in the design of high -voltage control circuit design. Using the four-way computing amplifier (OPA4130) and voltage reference (Ref3140), DAC7551-Q1 can generate width voltage fluctuations required to control the circuit.

Design requirements

Operation for ± 5-v:

For ± 10-v Operation:

Operation for ± 12-v:

Detailed design program

Use Formula 2 Calculate the output voltage of the configuration.

The fixed R1 and R2 resistors can be used to roughly set the gain required for the first paragraph of the equation. When R2 and R1 set the gain to include the smallest excess gain, you can use a single DAC7551-Q1 device to set the required offset voltage. Residual errors are not the problem of ring accuracy, because the offset and gain error can be tolerated. A DAC7551-Q1 device can provide VTail voltage, while the other four DAC7551Q1 devices can provide VDAC voltage to generate four high-voltage output. A SPI is enough to control all five DAC7551-Q1 devices in the chrysanthemum chain configuration.

Application curve

Power suggestion

The power supply applied to the VDD pin should be well adjusted and low noise. The output voltage of the switching power supply and the DC-DC converter often experiences high-frequency faults or peaks. In addition, digital components can produce high -frequency peaks similar to internal logic switches. This noise can easily be coupled to the DAC output voltage through the various paths between the power connection and the output. Like GND, the VDD pin should be connected to the trace wire power surface separated from the digital logic, until they are connected at the power entrance point. In addition, it is strongly recommended to use 1-μF and 10-μF capacitors and 0.1-μF bypass electrical containers. In some cases, additional bypass may be needed, such as 100 μF electrolytic capacitors, and even by electrical sensors and electricalsPi filter composed of containers.These bypass methods are designed for low -pass filtering and eliminating high -frequency noise.

Layout

Layout Guide

A precise simulation element needs to be carefully layout, enough bypass, and clean and well -adjusted power supply.The DAC7551-Q1 device provides single-power operation, which is usually used with digital logic, microcontroller, microprocessor, digital signal processor or combination.The more digital logic in the design, the higher the switch speed, the more difficult it is to prevent digital noise on the output end.Due to the single grounding pin of the DAC7551-Q1 device, all circuit currents (including DAC's numbers and simulation circuit currents) must flow through a single point.Ideally, GND should be directly connected to the simulation ground layer.This plane should be separated from the grounding connection of digital components until these components are connected at the power supply entrance of the system.

layout example