Features

14-bit resolution

2.4-GSPS maximum update rate digital modulus converter

dual differential differences Input port

-Data of the number/odd number of the number of unlike

-each port maximum 1.2-gsps, a total of 2.4-gsps

-Double 14-bit input+1 reference Bit

-DDR output clock

-DLL optimization clock timing time synchronized with the reference bit

-LVDS and super transportation #8482; voltage level compatibility

[[[

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123] -The internal 100Ω terminal used for data and reference digits

You can select 2 interpolations and fs/2 mixing

5 to 30 ma

1.2-v benchmark on the film

3.3-v simulation power operation

Power consumption: 2 w #8226; 252 Ball GDJ package

Application

Testing and measurement: Any waveform generator

Communication

Instructions explanatory

DAC5670

is a 14-bit 2.4-GSPS digital mode converter (DAC), which has a dual-reactive dual-dochest differential input port. DAC5670 runs at the DAC sampling rate, and the two input ports run at a maximum of 1.2 GSPS. An additional reference input sequence is delayed by the output clock used to adjust to the data source, and the internal data lock clock is optimized by delay locking ring (DLL) optimization. Alternatively, you can bypass the DLL and manage the timing interface by controlling data settings and keeping the time of DlyCLK.

DAC5670 can also receive data of up to 1.2GSPS on a input port configured at the same hour. In the single port mode, by repeating input sampling (only A U mode), two interpolations (only A_ZS mode) through zero -filling, or two interpolations (A_ONLY_INV) through repeated and reversing input samples, you can increase the input sampling rate Type of 2.4 GSPS.

DAC5670 uses a single 3-V to 3.6-V power supply voltage. Under the maximum working conditions, the power consumption is 2 watts. DAC5670 provides 20 mAh nominal full -standard full -scale differential current output, supporting single -end and differential applications. 1.2V temperature compensation band gap benchmark and control amplifier allows users to adjust the full marking output current from nominal 20 mAh toAs low as 5 mAh or up to 30 mA. The output current can directly supply the load without additional external output buffer. This device is designed for coupling output and 50Ω dual -end loads for differential transformers.

DAC5670 offers 252 ball GDJ packages. The feature is characterized by the temperature range of -40 ° C to 85 ° C.

Equipment information

(1), please refer to the appointment appendix at the end of the data table.

Simplified schematic diagrams

Typical features

Detailed detailed Explanation

Overview

FIG. 26 shows the simplified box diagram currently turning to DAC5670. The DAC5670 consists of a segment array of the NPN transistor current, which can provide a full -scale output current of up to 30 mAh. Differential current switches lead the current of each current to a complementary output node IOUT_P or IOUT 峎 N. The complementary current output can achieve differential operations, eliminating common modular noise sources (digital feedback, tablet and PCB noise), DC offset and even digital distortion components, and the signal output power doubles.

Full marking output current is set up by a combination of an external resistor (RBIAS) and the band gap benchmark voltage source (1.2V) and control amplifier. Internal mirrors through the resistance of RBIAS (IBIAS) to provide a full standard output current equivalent to 32 × IBIAS. By using the appropriate bias resistance value, the full marking current can be adjusted between 30 and 5 mA.

Figure Figure

Feature description

Digital input

DAC5670 Different Digital Input and LVDS and Super Transmission voltage electricity Compatible.

DAC5670 uses a low -voltage differential signal (LVDS and Super Transmission) as the bus input interface. LVDS and Hypertransport input modes have the characteristics of low difference volt voltage swing. The differences between LVDS and super transmission modes allow high -speed data transmission at low electromagnetic interference (EMI) levels. Figure 12 shows the equivalent complementary digital input interface of the DAC5670, which is suitable for pin DA_P [13: 0], DA_N [13: 0], DB_P [13: 0] and db_n [13: 0].

FIG. 13 shows the schematic diagram of the equivalent CMOS/TTL compatible digital input of DAC5670, which is suitable for the following pins: RESTART, LVDS_HTB,INV_CLK, Sleep, Normal, A_ONLY, A_ONLY_INV, A_ONLY_ZS.

DLL uses

DAC5670 at DAC sampling rate. The maximum running speed of each input port is 1.2GSPS. The DAC5670 provides an output clock (Dlylk) at half of the input port data rate (DACCLK/4) and monitor an additional reference bit (DTCLK). DTCLK adjusts the interface timing as the feedback clock. To achieve this, the DAC5670 realizes a DLL to help manage timing interfaces from external data sources. Like all DLLs, the ability of DLL in the length of the delay chain, the implementation of the phase detector, and the bandwidth of the control loop are limited. DAC5670 implements a orthodox phase detector. This scheme allows dynamic link libraries to provide the largest settings or keep delayed margin when reaching orthogonal intercourse. When the internal CLK/4 is 90 ° and the DTCLK phase is 90 °, orthogonal intercourse is reached. In addition, as the operating frequency decreases, the fixed length of the delay line limits its ability to change the delayed path to achieve orthogonal (see Figure 15). Please note that the delay line has asymmetric attributes. Negd range is less than POSD. From its name (restart) position, it can delay more than it minus.

FIG. 15 shows the behavior of the phase detector and the initial position of the rising edge of the phase detection and the delay line. There are four different quadrants to define behavior. Each quadrant represents the DDR clock rate (600 MHz under 2.4-GSPS). The ideal location is in the initial delay of DTCLK (so data bit). The stable locking point of the dynamic link library is between T/4, between Q1 and Q2. If the initial delay of DTCLK is at the quadrant 3 or 4, you can assert in Inv_CKPIN to improve the ability of DLL to obtain orthogonal. This assertion moves the stable accumulation to the center of 3T/4VS T/4, as shown in Figure 15. In essence, increasing the delayed area becomes a area that minus delay, and vice versa. CLK/4 clock phase will also reverse.

When the DLL is not suitable to manage the timing interface, when DLL is kept restarting, the fixed settings and maintenance of the DLYCLK output from the generated DlyCLK output. This is achieved by asserting the RESTART as a logic high and using the timing input conditions of the external timing interface when using the DLL. When using external settings and keeping time, users do not need to provide DTCLK. In this case, DTCLK should be biased towards effective LVDS levels (see Figure 3).

Settings/Keep your value is nonTo. In addition, setting/holding numbers may be delayed longer than DACCLK or DACCLK/2 cycles. To calculate the setting/maintenance value of the neighboring Dlyck conversion recently, the user must subtract the multiple of the DACLCK/2 cycle until the setting is less than the DACCLK/2 cycle. You can minus the same amount from the maintenance time. These new settings/retain values u200bu200bwill depend on the frequency.

Clock input

DAC5670 has a differential clock input compatible with LVPECL. FIG. 16 shows the equivalent diagram of the clock input buffer. The internal bias resistor sets the input co -mode voltage to AVDD/2, and the input resistance is usually 1K #8486; Various clock sources can be coupled with the device, including sine wave source (see Figure 17).

In order to obtain the best AC performance DAC5670, use differential LVPECL or sine wave source driving clock input, as shown in Figure 18 and 19. Here, the potential of the voltage transformer shall be set to the end -connect voltage required for the drive and the appropriate end -connected resistor (RT). The DAC5670 clock input can also use TTL/CMOS levels for single -end driving to obtain a lower clock rate (see Figure 20).

DAC transmission function

DAC5670 has a current remittance output. The current is controlled by dx_p [13: 0] and dx_n [13: 0] through iOUT_P and IOUT_N. In order to facilitate use, D [13: 0] is represented by the logical level equivalent of dx_p [13: 0] and its supplementary code dx_n [13: 0]. DAC5670 supports direct binary coding, D13 is MSB, and D0 is used as LSB. When all D [13: 0] input is set to high, the full marked current flows through iOutP; when all D [13: 0] input is set to low, the full marked current flows across iOutn. The relationship between iOut_P and IOUT 帴 N can be expressed as Formula 1.

The current is the full -standard output (5 mAh). Because the output level is a current remittance, the current can only flow into iOut 峎 N and IOUT_P pins from the AVDD through the AVDD.

The output current in each pin of the driving resistor load can be represented as Figure 21, Formula 2, and Formula 3.

Among the:

code is the decimal representation of the DAC input word

This is transformed into single -ended electricity at iOUT_N and IOUUT_PPressure, as shown in Formula 4 and Formula 5.

For example, assuming d [13: 0] u003d 1 and RL is 50 #8486;, then the differential voltage between the pins of iOut_n and IOUT_P can be represented as equal formulas. 6 to equation 8, where IO (FS) u003d 20 ma.

If D [13: 0] u003d 0, then iOUT_P u003d 0 MA, IOUT_N u003d 20 MA, differential voltage vdiff u003d –1 V.

output current and output voltage are complementary. Compared with each output separately, the voltage of differential measurement will double. Be careful not to exceed the compliance voltage of IOUT 峈 N and IOUT 峎 P pins to maintain low signal distortion.

Reference operation

DAC5670 includes the band gap benchmark and control amplifier for bias full -scale output current. Full margin output current has been set on the pin RBIASOUT and Rbiasin to set up an external resistor RBIAS. The bias current IBIAS, through the resistance RBIAS, is defined by the inventory voltage and control of the amplifier. Full margin output current is equal to 32 times the bias current. Therefore, the full marked output current iOUTF can be expressed as:

where:

pins of the vREFIO voltage at the REFIO and Refio_in [123 [123 ]

The gap reference voltage provides an accurate voltage of 1.2V. The designer should connect the 0.1 μF external REFIO filter capacitor to the REFIO and Refio_-in pins for compensation.

By changing the external resistance RBIAS, the full -standard output current can be adjusted from 30 mAh to 5 mAh.

Analog current output

FIG. 23 is a simplified schematic diagram of the current exchange array output with the corresponding switch. Differential NPN switches guide the current of each separate NPN current to the positive output node iOUT_P or its complementary negative output node iOUT_N. The input data displayed at DA_P [13: 0], DA_N [13: 0], DB_P [13: 0] and DB_N [13: 0] are decoded to control SW_P (N) and SW_N (N) current switches.

The external output resistance RLOAD is connected to the positive pole power AVDD.

DAC5670 can be easily configured to use the correct selected transformer to drive the two -terminal 50Ω cable. Figure 24 and 25 show the configuration of 1: 1 and 4: 1 respectively. These configurations provide the maximum inhibitory of the distortion of the co -modular noise sources and the dysfunction, so as toMake DAC's output power double. The center tap of the first side of the transformer is connected to the AVDD, so that both iOut 帴 n and IOUT 帴 p can get DC current.

Sleep mode

When the dormant pin was asserted (high), the DAC5670 entered the low power consumption mode.

Equipment function mode

Input format

DAC5670 has four input modes selected by four mutual configuration pins: normal, only A U, A U only u inV, and A u only u zs. Table 1 lists the input mode, input sampling rate, maximum DAC sampling rate (CLK input) and the generated DAC output sequence of each configuration. For all configurations, DlyCLK_P/N output and dtclk_p/n input are DACCLU P/N frequency divide by 4.

Application and implementation

Note

The information in the following application chapters is not part of the TI component specification. TI does not guarantee its accuracy Or integrity. TI's customers are responsible for determining the applicability of the component. Customers should verify and test their design implementation to confirm the system function.

Application information

DAC5670 is a 14 -bit DAC with a maximum input rate of 2.4 GSPS. DAC5670 is also suitable for working at a lower sampling rate without using DLL for input interface timing.

Typical application

Design requirements

This example uses a dacCLK rate of 2 GHz, and the signal output is 300 MHz.

Detailed design program

This example is a tone of 300 MHz with a sampling rate of 2-GHz. Data is applied to port A and B at a 1GHz dual data rate. The full marking output current is set to 19.2 mA.

Device settings:

low restart

LVDS U HTB

DLL locks the required inv_clk

Low sleep

Normal height

Only a_ low

only a_inv low

only low

dau p [0:13], da_n [ 0:13], db_p [0:13], Db_n [0:13], originated from the mode generator, generated 300 MHz tones, sampling depth 65536

Rbias 2 kΩ ground ground

Application curve

]

Power Suggestions

DAC5670 using a single 3.3V power supply simplifies the design requirements.The power supply should filter out any other system noise.Filter should pay special attention to the related frequency of output.

Layout

layout guide

DAC output terminal should be as close to the output as possible.

Keep RBIA a short route.

The decoupled power container should be as close to the power of the power as much as possible.

Digital differential input must be loose coupling of the ground, or the 100Ω differential coupling.

Digital differential input must match the length.

layout example