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2022-09-24 22:06:10
TMS320C6455BCTZA Yushenghong Electronics Hu Sheng: 13725538488
C6455 DSP integrates a large amount of on-chip memory to form a two-level storage system.
Level 1 (L1) program and data memory on the C6455 device is 32KB each. This memory can
Configured to map RAM, cache, or some combination of the two. When configured as cache, L1
Program (L1P) is a direct-mapped cache, where L1 Data (L1D) is a bidirectional set-associative cache. of
Level 2 (L2) memory is shared between program and data spaces and is 2048KB in size. L2 memory can
It can also be configured to map RAM, cache, or some combination of the two. C64x + Megamodule
There is also a 32-bit peripheral configuration (CFG) port, an internal DMA (IDMA) controller, a system
Components with reset/start control, interrupt/exception control, power-down control and free-running
32-bit timer for timestamp