PC435x/3x/2x/1x are Arm Cortex-M4 microcontrollers for embedded applications, containing an Arm Cortex-M0 coprocessor, up to 1 MB Flash and 136 kB on-chip SRAM, 16 kB EEPROM memory, four Channel SPI Flash Interface (SPIFI), advanced configurable peripherals such as Status Configurable Timer (SCT) and Serial General Purpose I/O (SGPIO) interface, two high-speed USB controllers, Ethernet, LCD, an external memory controller, and several digital and analog peripherals. The CPU frequency of LPC435x/3x/2x/1x can be up to 204 MHz.

Arm Cortex-M4 is a next-generation 32-bit core that provides system-enhancing features such as low power consumption, enhanced debug features and high-level block integration support. The Arm Cortex-M4 CPU contains a 3-stage pipeline, uses the Harvard architecture, with separate local instruction and data buses, a third bus for peripherals, and includes an internal prefetch unit that supports speculative branches. Arm Cortex-M4 supports single-cycle Digital signal processing and SIMD instructions. The kernel integrates a hardware floating point unit.

feature

Cortex-M4 processor core

Arm Cortex-M4 processor up to 204 MHz

Arm Cortex-M4 built-in Memory Protection Unit (MPU) supporting 8 banks

Arm Cortex-M4 built-in Nestable Vectored Interrupt Controller (NVIC)

hardware floating point unit

Non-maskable interrupt (NMI) input

JTAG and serial debug (SWD), serial trace, eight breakpoints, and four watchpoints

Enhanced Trace Module (ETM) and Enhanced Trace Buffer (ETB) support

System Tick Timer

Cortex-M0 processor core

Arm Cortex-M0 coprocessor loads Arm Cortex-M4 main application processor

Operating frequency up to 204 MHz

JTAG

Built-in NVIC

On-chip memory

Up to 1 MB on-chip dual flash memory with flash accelerator

16 kB on-chip EEPROM data memory

136 kB SRAM for code and data

Supports multiple SRAM blocks with independent bus access. Both SRAM blocks can be powered down independently

64 kB ROM with boot code and on-chip software drivers

64-bit general-purpose one-time programmable (OTP) memory

Configurable digital peripherals

Serial GPIO (SGPIO) interface

State Configurable Timer (SCT) Subsystem on AHB

Global Multiple Input Array (GIMA) allows cross-connection of multiple inputs and outputs of event-driven peripherals such as timers, SCT, and ADC0/1

serial interface

Quad SPI Flash Interface (SPIFI) with four lanes up to 52 MB/s

Support RMII interface and MII interface, 10/100T Ethernet MAC with DMA to achieve high throughput under low CPU load. Supports IEEE 1588 Timestamp/Advanced Timestamp (IEEE 1588-2008 v2)

One high-speed USB 2.0 host/device/OTG interface with on-chip high-speed PHY with DMA support

A high-speed USB 2.0 host/device interface with DMA support, with on-chip high-speed PHY and external high-speed PHY ULPI interface

USB interface electronics test software included in the ROM USB stack

A 550 UART with DMA support and full modem interface

Three 550 USARTs with DMA and isochronous mode support have a smart card interface compliant with the ISO7816 standard specification. One USART with IrDA interface

Up to two C_CAN 2.0B controllers with one channel each. Operation of all other peripherals connected to the same bus bridge is not included when using the C_CAN controller

Two SSP controllers with FIFO and multi-protocol capabilities. Both SSPs support DMA

an SPI controller

An ultra-fast I2C-bus interface with monitor mode and open-drain I/O pins fully compliant with the I2C-bus specification. Supports data rates up to 1 Mbit/s

A standard I2C bus interface with monitor mode and standard I/O pins

Two I2S interfaces, one with DMA support and one with 1 input and 1 output.

digital peripherals

External Memory Controller (EMC) supporting external SRAM, ROM, NOR Flash and SDRAM devices

LCD controller with DMA support and a programmable display resolution up to 1024H × 768V. Supports monochrome and color STN panels and TFT color panels; supports 1/2/4/8 bpp Color Lookup Table (CLUT) and 16/24-bit direct pixel mapping. LPC4357/53 devices only

Secure Digital Input Output (SD/MMC) Card Interface

Eight-channel general-purpose DMA controller to access all memories on the AHB bus and all DMA-capable AHB slaves

Up to 164 general-purpose input/output (GPIO) pins with configurable pull-up/pull-down resistors

The GPIO registers are located on the AHB for quick access. GPIO port supports DMA

Up to eight of all GPIO pins can be used as edge- and level-triggered interrupt sources

Two GPIO group interrupt modules can realize interrupts in programmable format based on the input state of a group of GP input and output pins

Four general-purpose timers/counters with capture and match

1 Motor Control Pulse Width Modulator (PWM) for 3-Phase Motor Control

1 Quadrature Encoder Interface (QEI)

Repeated Interrupt Timer (RI Timer)

Windowed Watchdog Timer (WWDT)

Ultra-low-power real-time clock (RTC) on separate power domain with 256-byte battery-backed backup registers

Alarm timer; battery powered

Analog peripherals

One 10-bit DAC with DMA support, data conversion rate up to 400 kSamples/s

Two 10-bit ADCs with DMA support and data conversion rates up to 400 kSamples/s. Up to eight input channels per ADC

Each device has a unique ID

clock generation unit

Crystal oscillators operating from 1 MHz to 25 MHz

12 MHz internal RC oscillator calibrated to 2% accuracy (1 % at Tamb = 0 °C to 85 °C) over full temperature and voltage range

Ultra Low Power Real Time Clock (RTC) Crystal Oscillator

Three on-chip PLLs allow the CPU to run at maximum CPU speed without the need for a high-frequency crystal. The second PLL can be used for Hi-Speed USB and the third PLL can be used as an audio PLL

clock output

power supply

Single 3.3 V (2.2 V to 3.6 V) supply with on-chip DC-DC converter for core power and RTC power domains

RTC power domain can be powered by 3 V battery alone

Four low-power modes: sleep mode, deep-sleep mode, power-down mode, and deep power-down mode

The processor wakes up from sleep mode through wakeup interrupts from different peripherals

Wake-up from deep-sleep, power-down, and deep power-down modes via external interrupts and interrupts generated by the battery-powered block of the RTC power domain

Brownout detection with four independent thresholds that can trigger interrupts and force resets

Power-On Reset (POR)

Available in LQFP208, LQFP144, LBGA256 or TFBGA100 packages

target application

motor control

power management

large appliances

RFID Card Reader

Embedded Audio Applications

automated industry

Electronic metering